11 Replies Latest reply on Jan 4, 2019 4:42 PM by dan_liddell

    LVS BOX does not bypass subckt for custom cell

    rcy22

      To whom it may concern,

       

      I have designed my own inductor using EMX with ports and an extracted DC model of a resistor between the IN and OUT ports of the inductor.

       

      My process includes a RES layer which isolates the IN and OUT of otherwise shorted strip of metal. However, when I run LVS with the LVS BOX function for SOURCE and LAYOUT I still get a warning box that states:
      "source netlist references but does not define 1 subckt: ind_bal_100p"

       

       

      My understanding from reading the SVRF documentation from MentorGraphics PDK was that the LVS BOX command would cause LVS to not look for the ind_bal_100p netlist. Am I missing something?

       

      thank you

        • 1. Re: LVS BOX does not bypass subckt for custom cell
          dan_liddell

          Please show the SPICE syntaxes from layout and source that are being matched.

           

          dan

          • 2. Re: LVS BOX does not bypass subckt for custom cell
            rcy22

            from .sp (layout):

             

             

            from netlist:

            • 3. Re: LVS BOX does not bypass subckt for custom cell
              chris_balcom

              I think you will see this same error regardless of LVS BOX usage:

               

              ...when I run LVS with the LVS BOX function for SOURCE and LAYOUT I still get a warning box that states:

              "source netlist references but does not define 1 subckt: ind_bal_100p"

               

              I believe that warning/error indicates the subckt definition for ind_bal_100p is not actually found or available during the source netlist readin. In other words, it's as if the subckt snippet you described, isn't actually available during the LVS run, as if the file you're showing isn't actually being included.

               

              Another way to describe this is that I don't think LVS BOX statements will allow the initial netlist parsing to bypass missing subckts that are referenced. Once you have a source netlist that includes all the subckts that are referenced (such as by using .include statements for library cells) then after that point you might consider the effect of LVS BOX statements to ignore the devices contained within box cells.

               

              Best regards,

              -chris

              • 4. Re: LVS BOX does not bypass subckt for custom cell
                rcy22

                Thank you for the response.

                 

                Does that mean I should write my own netlist in an include file? Do you have an example of this?

                • 5. Re: LVS BOX does not bypass subckt for custom cell
                  rcy22

                  Interesting new discovery:

                   

                  If I change all layers of metal in my layout to be the topmost metal, I can pass LVS. However, to have an inductor with more than 1 turn or any transformers, multiple metals must be used. Does anyone have experience with passing LVS using LVS box (or any other method) for custom inductors/transformers?

                  • 6. Re: LVS BOX does not bypass subckt for custom cell
                    chris_balcom

                    I just mean to say that it seems the netlist portion you showed, with the subckt definition, doesn't actually seem to be part of your netlist that is being used for LVS. Maybe you are using the wrong netlist or an incomplete netlist?

                    • 7. Re: LVS BOX does not bypass subckt for custom cell
                      dan_liddell

                      To address a previous thought, the LVS Box statement does not cause the specified subcircuit to be ignored, it causes the contents of a subcircuit to be ignored. From the SVRF Manual:

                       

                      "Hierarchical LVS comparison ignores the contents of specified box cells when it reads the layout or source netlists, essentially comparing box cells as primitive devices with pins."

                       

                      If a specified box cell cannot be found in the layout or source, or if a called subcircuit definition is missing (which appears to be the case here), a warning of some kind will be issued. Even with your modified layout, the source should still trigger a warning as before, assuming the source netlist didn't change.

                       

                      As Chris mentions later in the thread, the root cause of the problem appears to be an improper source netlist. A simple test for a remedy is to create a file with just the source .subckt definition for ind_bal_100p. Then include that file from the Source Path netlist by adding a ".include" statement referencing the new file. If that clears the netlist warning, you at least have a confirmation of the root cause of the warning message.

                       

                      If you have access to Support Center, this article may have some relevance to the problem:

                       

                      https://support.mentor.com/en/product/852852053/knowledge-base/MG28769

                       

                      We haven't discussed which other tools are in your flow, so the exact details in the article may only loosely resemble your verification environment.

                      • 8. Re: LVS BOX does not bypass subckt for custom cell
                        rcy22

                        Hi,

                         

                        Thank you for your clarification. This is actually what I did at the very beginning (before I posted to MentorGraphics). I created the subcircuit file for each custom inductor (generated by EMX). In the calibre--> setup--> Netlist Export I include the custom inductors file.

                         

                        When I run LVS however, I am left with lvsres in the schematic but no corresponding component in the layout. This is why I drew the RES layer and arrived at the problem mentioned above. To summarize, I already have the additional netlist being included, and that has not solved the problem.

                         

                        Hopefully this clarifies the issue that I am facing.

                        • 9. Re: LVS BOX does not bypass subckt for custom cell
                          dan_liddell

                          OK. So it sounds like the source netlist is now complete and there are no warnings about missing subcircuits. If that is false, then all bets are off moving forward.

                           

                          Please remove any LVS Box statements related to your inductor circuit, run LVS-H comparison, and then post the discrepancy listed in the LVS Report showing the layout and source elements that LVS attempted to match.

                          • 10. Re: LVS BOX does not bypass subckt for custom cell
                            rcy22

                            LVS Netlist Compiler - Errors and Warnings for "/research/MOLNAR/rcy22_IBM/ind_bal_100p.src.net"

                            ------------------------------------------------------------------------------------------------

                             

                             

                            Warning: Duplicate subckt definition "ind_bal_100p" at line 24 in file "/research/MOLNAR/rcy22_IBM/ind_bal_100p.src.net"

                                     previously defined at line 1 in file "./include_ind_bal_100p.cal"

                             

                             

                             

                             

                             

                             

                             

                             

                                              ##################################################

                                              ##                                              ##

                                              ##         C A L I B R E    S Y S T E M         ##

                                              ##                                              ##

                                              ##             L V S   R E P O R T              ##

                                              ##                                              ##

                                              ##################################################

                             

                             

                             

                             

                             

                             

                            REPORT FILE NAME:         ind_bal_100p.lvs.report

                            LAYOUT NAME:              /research/MOLNAR/rcy22_IBM/ind_bal_100p.sp ('ind_bal_100p')

                            SOURCE NAME:              /research/MOLNAR/rcy22_IBM/ind_bal_100p.src.net ('ind_bal_100p')

                            RULE FILE:                /research/MOLNAR/rcy22_IBM/_bicmos8hp.lvs.cal_

                            CREATION TIME:            Fri Jan  4 14:19:20 2019

                            CURRENT DIRECTORY:        /research/MOLNAR/rcy22_IBM

                            USER NAME:                rcy22

                            CALIBRE VERSION:          v2018.2_41.34    Fri Aug 3 14:23:24 PDT 2018

                             

                             

                             

                             

                             

                             

                                                           OVERALL COMPARISON RESULTS

                             

                             

                             

                             

                             

                             

                                              #   #         ##################### 

                                               # #          #                   # 

                                                #           #     INCORRECT     # 

                                               # #          #                   # 

                                              #   #         ##################### 

                             

                             

                             

                             

                              Error:    Different numbers of instances.

                             

                             

                             

                             

                            **************************************************************************************************************

                                                                  CELL  SUMMARY

                            **************************************************************************************************************

                             

                             

                              Result         Layout                        Source

                              -----------    -----------                   --------------

                              INCORRECT      ind_bal_100p                  ind_bal_100p

                             

                             

                             

                             

                             

                             

                            **************************************************************************************************************

                                                                  LVS PARAMETERS

                            **************************************************************************************************************

                             

                             

                             

                             

                            o LVS Setup:

                             

                             

                               LVS COMPONENT TYPE PROPERTY            element

                               LVS COMPONENT SUBTYPE PROPERTY         model

                               LVS PIN NAME PROPERTY                  phy_pin

                               LVS POWER NAME                         "VDD" "Vdd" "vdd" "VDD:P" "DVDD" "DVDD:P" "VDD!" "?VDD?" "Vdd?" "?vdd?" "inh_vdd"

                                                                      "INH_VDD" "VCC" "Vcc" "vcc" "?VCC?" "?vcc?"

                               LVS GROUND NAME                        "VSS" "Vss" "vss" "VSS:G" "DVSS" "DVSS:P" "?VSS?" "vss?" "GND" "GND:G" "GND!" "?GND?"

                                                                      "gnd" "gnd?" "sub!" "?sub?" "inh_gnd" "INH_GND" "GN?" "GN1" "GP" "GN2"

                               LVS CELL SUPPLY                        NO

                               LVS RECOGNIZE GATES                    NONE

                               LVS IGNORE PORTS                       NO

                               LVS CHECK PORT NAMES                   YES

                               LVS IGNORE TRIVIAL NAMED PORTS         NO

                               LVS BUILTIN DEVICE PIN SWAP            NO

                               LVS ALL CAPACITOR PINS SWAPPABLE       NO

                               LVS DISCARD PINS BY DEVICE             NO

                               LVS SOFT SUBSTRATE PINS                NO

                               LVS INJECT LOGIC                       NO

                               LVS EXPAND UNBALANCED CELLS            YES

                               LVS FLATTEN INSIDE CELL                NO

                               LVS EXPAND SEED PROMOTIONS             NO

                               LVS PRESERVE PARAMETERIZED CELLS       NO

                               LVS GLOBALS ARE PORTS                  YES

                               LVS REVERSE WL                         NO

                               LVS SPICE PREFER PINS                  NO

                               LVS SPICE SLASH IS SPACE               YES

                               LVS SPICE ALLOW FLOATING PINS          YES

                               LVS SPICE ALLOW INLINE PARAMETERS      NO

                               LVS SPICE ALLOW UNQUOTED STRINGS       NO

                               LVS SPICE CONDITIONAL LDD              NO

                               LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO

                               // LVS SPICE EXCLUDE CELL SOURCE

                               // LVS SPICE EXCLUDE CELL LAYOUT

                               LVS SPICE IMPLIED MOS AREA             NO

                               // LVS SPICE MULTIPLIER NAME

                               LVS SPICE OVERRIDE GLOBALS             NO

                               LVS SPICE REDEFINE PARAM               NO

                               LVS SPICE REPLICATE DEVICES            YES

                               LVS SPICE SCALE X PARAMETERS           NO

                               LVS SPICE STRICT WL                    YES

                               // LVS SPICE OPTION

                               LVS STRICT SUBTYPES                    NO

                               LVS EXACT SUBTYPES                     NO

                               LAYOUT CASE                            YES

                               SOURCE CASE                            YES

                               LVS COMPARE CASE                       NO

                               LVS DOWNCASE DEVICE                    NO

                               LVS REPORT MAXIMUM                     ALL

                               LVS PROPERTY RESOLUTION MAXIMUM        ALL

                               // LVS SIGNATURE MAXIMUM

                               LVS FILTER UNUSED OPTION               AB AC AD B D O RC RD RE RF RG S YB ZB

                               LVS REPORT OPTION                      E S V

                               LVS REPORT UNITS                       YES

                               // LVS NON USER NAME PORT

                               // LVS NON USER NAME NET

                               // LVS NON USER NAME INSTANCE

                               // LVS IGNORE DEVICE PIN

                               // LVS PREFER NETS FILTER SOURCE

                               // LVS PREFER NETS FILTER LAYOUT

                             

                             

                               // Reduction

                             

                             

                               LVS REDUCE SERIES MOS                  NO

                               LVS REDUCE PARALLEL MOS                YES

                               LVS REDUCE SEMI SERIES MOS             NO

                               LVS REDUCE SPLIT GATES                 NO

                               LVS REDUCE PARALLEL BIPOLAR            NO

                               LVS REDUCE SERIES CAPACITORS           NO

                               LVS REDUCE PARALLEL CAPACITORS         YES

                               LVS REDUCE SERIES RESISTORS            YES

                               LVS REDUCE PARALLEL RESISTORS          YES

                               LVS REDUCE PARALLEL DIODES             YES

                             

                             

                               LVS REDUCE  Q(npn)  PARALLEL [ TOLERANCE exl 0 exw 0 nstripes 0 hb 0 rel 0 mSwitch 0 ]

                               LVS REDUCE  npnt  PARALLEL [ TOLERANCE exl 0 exw 0 nstripes 0 hb 0 rel 0 mSwitch 0 ]

                               LVS REDUCE  Q(npnxp)  PARALLEL [ TOLERANCE exl 0 exw 0 nstripes 0 hb 0 rel 0 mSwitch 0 ]

                               LVS REDUCE  npnxpt  PARALLEL [ TOLERANCE exl 0 exw 0 nstripes 0 hb 0 rel 0 mSwitch 0 ]

                               LVS REDUCE  singlewire  SERIES va vb [ TOLERANCE w 0 shieldads 0 s 0 layerads 0 overads 0 ]

                               LVS REDUCE  singlecpw  SERIES va vb [ TOLERANCE w 0 s 0 layer_sig 0 ]

                               LVS REDUCE  R(opndres)  SERIES POS NEG [ TOLERANCE w 0 pbar 0 ]

                               LVS REDUCE  R(oppdres)  SERIES POS NEG [ TOLERANCE w 0 pbar 0 ]

                               LVS REDUCE  R(sblkndres)  SERIES POS NEG [ TOLERANCE w 0 sbar 0 ]

                               LVS REDUCE  R(sblkpdres)  SERIES POS NEG [ TOLERANCE w 0 pbar 0 ]

                               LVS REDUCE  R(opppcres)  SERIES POS NEG [ TOLERANCE w 0 bp 0 pbar 0 l 0 ]

                               LVS REDUCE  R(oprrpres)  SERIES POS NEG [ TOLERANCE w 0 bp 0 pbar 0 ]

                               LVS REDUCE  R(kqres)  SERIES POS NEG [ TOLERANCE w 0 pbar 0 ]

                               LVS REDUCE  R(nsres)  SERIES POS NEG [ TOLERANCE w 0 pbar 0 ]

                               LVS REDUCE  R(lvsres)  SERIES POS NEG

                               LVS REDUCE  R(lvsres)  PARALLEL

                               LVS REDUCE  R(opndres)  PARALLEL [ TOLERANCE l 0 sbar 0 mSwitch 0 ]

                               LVS REDUCE  R(oppdres)  PARALLEL [ TOLERANCE l 0 s 0 mSwitch 0 ]

                               LVS REDUCE  R(sblkndres)  PARALLEL [ TOLERANCE l 0 sbar 0 ]

                               LVS REDUCE  R(sblkpdres)  PARALLEL [ TOLERANCE l 0 s 0 ]

                               LVS REDUCE  R(opppcres)  PARALLEL [ TOLERANCE l 0 bp 0 sbar 0 mSwitch 0 ]

                               LVS REDUCE  R(oprrpres)  PARALLEL [ TOLERANCE l 0 bp 0 sbar 0 mSwitch 0 ]

                               LVS REDUCE  R(kqres)  PARALLEL [ TOLERANCE l 0 sbar 0 bp 0 mSwitch 0 ]

                               LVS REDUCE  R(nsres)  PARALLEL [ TOLERANCE l 0 sbar 0 mSwitch 0 ]

                               LVS REDUCE  c(mim)  PARALLEL [ TOLERANCE l 0 w 0 bp 0 mSwitch 0 ]

                               LVS REDUCE  c(dualmim)  PARALLEL [ TOLERANCE l 0 w 0 bp 0 mSwitch 0 ]

                               LVS REDUCE  D(havar)  PARALLEL [ TOLERANCE l 0 w 0 nf 0 mSwitch 0 ]

                               LVS REDUCE  diffhavar  PARALLEL [ TOLERANCE l 0 w 0 nf 0 mSwitch 0 ]

                               LVS REDUCE  diffncap  PARALLEL [ TOLERANCE w 0 l 0 nrep 0 mSwitch 0 ]

                               LVS REDUCE  D(sbd)  PARALLEL [ TOLERANCE w 0 l 0 nf 0 mSwitch 0 ]

                               LVS REDUCE  D(pin)  PARALLEL [ TOLERANCE mSwitch 0 w 0 l 0 nf 0 wca 0 ]

                               LVS REDUCE  Q(esdvpnp)  PARALLEL [ TOLERANCE nf 0 ]

                               LVS REDUCE  esdvpnp_t3  PARALLEL [ TOLERANCE nf 0 ]

                               LVS REDUCE  esdvnpn  PARALLEL [ TOLERANCE nf 0 ]

                               LVS REDUCE  esdnsh_base  PARALLEL NO

                               LVS REDUCE  esdpsh_base  PARALLEL NO

                               LVS REDUCE  D(esdndsx)  PARALLEL [ TOLERANCE nf 0 ]

                               LVS REDUCE  D(esdnwsx)  PARALLEL [ TOLERANCE nf 0 bp 0 ]

                               LVS REDUCE  D(esdpnpi)  PARALLEL

                               LVS REDUCE  D(esdndpi)  PARALLEL

                               LVS REDUCE  D(dipdnw)  PARALLEL [ TOLERANCE w 0 l 0 ]

                               LVS REDUCE  D(var)  PARALLEL [ TOLERANCE w 0 l 0 ]

                               LVS REDUCE  Q(divpnp)  PARALLEL [ TOLERANCE nf 0 w 0 l 0 m 0 par 0 mSwitch 0 ]

                               LVS REDUCE  vpnpsx  PARALLEL [ TOLERANCE nstripes 0 evw 0 evl 0 ccr 0 ]

                               LVS REDUCE  tdndsx  PARALLEL

                               LVS REDUCE  D(tdpdnw)  PARALLEL

                               LVS REDUCE  ncap  PARALLEL [ TOLERANCE w 0 l 0 nrep 0 mswitch 0 ]

                               LVS REDUCE  dgncap  PARALLEL [ TOLERANCE w 0 l 0 nrep 0 mswitch 0 ]

                               LVS REDUCE  SUBC  PARALLEL

                               LVS REDUCE  efuse  PARALLEL

                               LVS REDUCE  MN(nfet_rf)  PARALLEL [ TOLERANCE l 0 ngcon 0 nf 0 gtab 0 m 0 ]

                               LVS REDUCE  MN(nfet33_rf)  PARALLEL [ TOLERANCE l 0 ngcon 0 nf 0 gtab 0 m 0 ]

                               LVS REDUCE  MP(pfet_rf)  PARALLEL [ TOLERANCE l 0 ngcon 0 nf 0 gtab 0 m 0 ]

                               LVS REDUCE  MN(nfet)  PARALLEL [ TOLERANCE l 2 ngcon 0 m 0 mSwitch 0 ]

                               LVS REDUCE  MP(pfet)  PARALLEL [ TOLERANCE l 2 ngcon 0 m 0 mSwitch 0 ]

                               LVS REDUCE  MN(nfet33)  PARALLEL [ TOLERANCE l 2 ngcon 0 m 0 mSwitch 0 ]

                               LVS REDUCE  MP(pfet33)  PARALLEL [ TOLERANCE l 2 ngcon 0 m 0 mSwitch 0 ]

                               LVS REDUCE  MD(dgnfet_rf)  PARALLEL [ TOLERANCE l 0 ngcon 0 nf 0 gtab 0 m 0 ]

                               LVS REDUCE  MD(dgpfet_rf)  PARALLEL [ TOLERANCE l 0 ngcon 0 nf 0 gtab 0 m 0 ]

                               LVS REDUCE  MP(pfet33_rf)  PARALLEL [ TOLERANCE l 0 ngcon 0 nf 0 gtab 0 m 0 ]

                               LVS REDUCE  MD(dgnfet)  PARALLEL [ TOLERANCE l 2 ngcon 0 m 0 mSwitch 0 ]

                               LVS REDUCE  MD(dgpfet)  PARALLEL [ TOLERANCE l 2 ngcon 0 m 0 mSwitch 0 ]

                               LVS REDUCE  nfettw  PARALLEL [ TOLERANCE l 0 ngcon 0 mSwitch 0 m 0 t3well 0 gns 0 ]

                               LVS REDUCE  nfet33tw  PARALLEL [ TOLERANCE l 0 ngcon 0 mSwitch 0 m 0 t3well 0 gns 0 ]

                               LVS REDUCE  dgnfettw  PARALLEL [ TOLERANCE l 0 ngcon 0 mSwitch 0 m 0 t3well 0 gns 0 ]

                               LVS REDUCE  nfettw_rf  PARALLEL [ TOLERANCE l 0 ngcon 0 nf 0 gtab 0 m 0 mSwitch 0 t3well 0 gns 0 ]

                               LVS REDUCE  dgnfettw_rf  PARALLEL [ TOLERANCE l 0 ngcon 0 nf 0 gtab 0 m 0 mSwitch 0 t3well 0 gns 0 ]

                               LVS REDUCE  nfet33tw_rf  PARALLEL [ TOLERANCE l 0 ngcon 0 nf 0 gtab 0 m 0 mSwitch 0 t3well 0 gns 0 ]

                               LVS REDUCTION PRIORITY                 PARALLEL

                              

                               LVS SHORT EQUIVALENT NODES             NO

                             

                             

                               // Filter

                             

                             

                               LVS FILTER  C(CP)  OPEN

                               LVS FILTER  R(RP)  SHORT

                             

                             

                               // Trace Property

                             

                             

                               TRACE PROPERTY  mn(nfet)  w w 2

                               TRACE PROPERTY  mn(nfet)  l l 2

                               TRACE PROPERTY  mn(nfet)  nf nf 0

                               TRACE PROPERTY  mn(nfet)  m m 0

                               TRACE PROPERTY  mn(nfet)  par par 0

                               TRACE PROPERTY  mn(nfet)  ngcon ngcon 0

                               TRACE PROPERTY  nfettw  w w 0.5

                               TRACE PROPERTY  nfettw  l l 0.5

                               TRACE PROPERTY  nfettw  nf nf 0

                               TRACE PROPERTY  nfettw  m m 0

                               TRACE PROPERTY  nfettw  par par 0

                               TRACE PROPERTY  nfettw  ngcon ngcon 0

                               TRACE PROPERTY  nfettw  gns gns 0

                               TRACE PROPERTY  mn(nfet33)  w w 2

                               TRACE PROPERTY  mn(nfet33)  l l 2

                               TRACE PROPERTY  mn(nfet33)  nf nf 0

                               TRACE PROPERTY  mn(nfet33)  m m 0

                               TRACE PROPERTY  mn(nfet33)  par par 0

                               TRACE PROPERTY  mn(nfet33)  ngcon ngcon 0

                               TRACE PROPERTY  nfet33tw  w w 0.5

                               TRACE PROPERTY  nfet33tw  l l 0.5

                               TRACE PROPERTY  nfet33tw  nf nf 0

                               TRACE PROPERTY  nfet33tw  m m 0

                               TRACE PROPERTY  nfet33tw  par par 0

                               TRACE PROPERTY  nfet33tw  ngcon ngcon 0

                               TRACE PROPERTY  nfet33tw  gns gns 0

                               TRACE PROPERTY  md(dgnfet)  w w 0.5

                               TRACE PROPERTY  md(dgnfet)  l l 0.5

                               TRACE PROPERTY  md(dgnfet)  nf nf 0

                               TRACE PROPERTY  md(dgnfet)  m m 0

                               TRACE PROPERTY  md(dgnfet)  par par 0

                               TRACE PROPERTY  md(dgnfet)  ngcon ngcon 0

                               TRACE PROPERTY  dgnfettw  w w 0.5

                               TRACE PROPERTY  dgnfettw  l l 0.5

                               TRACE PROPERTY  dgnfettw  nf nf 0

                               TRACE PROPERTY  dgnfettw  m m 0

                               TRACE PROPERTY  dgnfettw  par par 0

                               TRACE PROPERTY  dgnfettw  ngcon ngcon 0

                               TRACE PROPERTY  dgnfettw  gns gns 0

                               TRACE PROPERTY  md(dgpfet)  w w 0.5

                               TRACE PROPERTY  md(dgpfet)  l l 0.5

                               TRACE PROPERTY  md(dgpfet)  nf nf 0

                               TRACE PROPERTY  md(dgpfet)  m m 0

                               TRACE PROPERTY  md(dgpfet)  par par 0

                               TRACE PROPERTY  md(dgpfet)  ngcon ngcon 0

                               TRACE PROPERTY  mp(pfet)  w w 2

                               TRACE PROPERTY  mp(pfet)  l l 2

                               TRACE PROPERTY  mp(pfet)  nf nf 0

                               TRACE PROPERTY  mp(pfet)  m m 0

                               TRACE PROPERTY  mp(pfet)  par par 0

                               TRACE PROPERTY  mp(pfet)  ngcon ngcon 0

                               TRACE PROPERTY  mp(pfet33)  w w 2

                               TRACE PROPERTY  mp(pfet33)  l l 2

                               TRACE PROPERTY  mp(pfet33)  nf nf 0

                               TRACE PROPERTY  mp(pfet33)  m m 0

                               TRACE PROPERTY  mp(pfet33)  par par 0

                               TRACE PROPERTY  mp(pfet33)  ngcon ngcon 0

                               TRACE PROPERTY  mn(nfet_rf)  w w 0.5

                               TRACE PROPERTY  mn(nfet_rf)  l l 0.5

                               TRACE PROPERTY  mn(nfet_rf)  nf nf 0

                               TRACE PROPERTY  mn(nfet_rf)  m m 0

                               TRACE PROPERTY  mn(nfet_rf)  par par 0

                               TRACE PROPERTY  mn(nfet_rf)  gtab gtab 0

                               TRACE PROPERTY  mn(nfet_rf)  ngcon ngcon 0

                               TRACE PROPERTY  mn(nfet33_rf)  w w 0.5

                               TRACE PROPERTY  mn(nfet33_rf)  l l 0.5

                               TRACE PROPERTY  mn(nfet33_rf)  nf nf 0

                               TRACE PROPERTY  mn(nfet33_rf)  m m 0

                               TRACE PROPERTY  mn(nfet33_rf)  par par 0

                               TRACE PROPERTY  mn(nfet33_rf)  gtab gtab 0

                               TRACE PROPERTY  mn(nfet33_rf)  ngcon ngcon 0

                               TRACE PROPERTY  md(dgnfet_rf)  w w 0.5

                               TRACE PROPERTY  md(dgnfet_rf)  l l 0.5

                               TRACE PROPERTY  md(dgnfet_rf)  nf nf 0

                               TRACE PROPERTY  md(dgnfet_rf)  m m 0

                               TRACE PROPERTY  md(dgnfet_rf)  par par 0

                               TRACE PROPERTY  md(dgnfet_rf)  ngcon ngcon 0

                               TRACE PROPERTY  md(dgnfet_rf)  gtab gtab 0

                               TRACE PROPERTY  nfettw_rf  w w 0.5

                               TRACE PROPERTY  nfettw_rf  l l 0.5

                               TRACE PROPERTY  nfettw_rf  nf nf 0

                               TRACE PROPERTY  nfettw_rf  m m 0

                               TRACE PROPERTY  nfettw_rf  par par 0

                               TRACE PROPERTY  nfettw_rf  gtab gtab 0

                               TRACE PROPERTY  nfettw_rf  ngcon ngcon 0

                               TRACE PROPERTY  nfettw_rf  gns gns 0

                               TRACE PROPERTY  nfet33tw_rf  w w 0.5

                               TRACE PROPERTY  nfet33tw_rf  l l 0.5

                               TRACE PROPERTY  nfet33tw_rf  nf nf 0

                               TRACE PROPERTY  nfet33tw_rf  m m 0

                               TRACE PROPERTY  nfet33tw_rf  par par 0

                               TRACE PROPERTY  nfet33tw_rf  gtab gtab 0

                               TRACE PROPERTY  nfet33tw_rf  ngcon ngcon 0

                               TRACE PROPERTY  nfet33tw_rf  gns gns 0

                               TRACE PROPERTY  dgnfettw_rf  w w 0.5

                               TRACE PROPERTY  dgnfettw_rf  l l 0.5

                               TRACE PROPERTY  dgnfettw_rf  nf nf 0

                               TRACE PROPERTY  dgnfettw_rf  m m 0

                               TRACE PROPERTY  dgnfettw_rf  par par 0

                               TRACE PROPERTY  dgnfettw_rf  ngcon ngcon 0

                               TRACE PROPERTY  dgnfettw_rf  gtab gtab 0

                               TRACE PROPERTY  dgnfettw_rf  gns gns 0

                               TRACE PROPERTY  mp(pfet_rf)  w w 0.5

                               TRACE PROPERTY  mp(pfet_rf)  l l 0.5

                               TRACE PROPERTY  mp(pfet_rf)  nf nf 0

                               TRACE PROPERTY  mp(pfet_rf)  m m 0

                               TRACE PROPERTY  mp(pfet_rf)  par par 0

                               TRACE PROPERTY  mp(pfet_rf)  gtab gtab 0

                               TRACE PROPERTY  mp(pfet_rf)  ngcon ngcon 0

                               TRACE PROPERTY  md(dgpfet_rf)  w w 0.5

                               TRACE PROPERTY  md(dgpfet_rf)  l l 0.5

                               TRACE PROPERTY  md(dgpfet_rf)  nf nf 0

                               TRACE PROPERTY  md(dgpfet_rf)  m m 0

                               TRACE PROPERTY  md(dgpfet_rf)  par par 0

                               TRACE PROPERTY  md(dgpfet_rf)  ngcon ngcon 0

                               TRACE PROPERTY  md(dgpfet_rf)  gtab gtab 0

                               TRACE PROPERTY  mp(pfet33_rf)  w w 0.5

                               TRACE PROPERTY  mp(pfet33_rf)  l l 0.5

                               TRACE PROPERTY  mp(pfet33_rf)  nf nf 0

                               TRACE PROPERTY  mp(pfet33_rf)  m m 0

                               TRACE PROPERTY  mp(pfet33_rf)  par par 0

                               TRACE PROPERTY  mp(pfet33_rf)  ngcon ngcon 0

                               TRACE PROPERTY  mp(pfet33_rf)  gtab gtab 0

                               TRACE PROPERTY  r(opppcres)  w w 1

                               TRACE PROPERTY  r(opppcres)  l l 1

                               TRACE PROPERTY  r(opppcres)  sbar sbar 0

                               TRACE PROPERTY  r(opppcres)  pbar pbar 0

                               TRACE PROPERTY  r(opppcres)  bp bp 0

                               TRACE PROPERTY  r(opppcres)  m m 0

                               TRACE PROPERTY  r(opppcres)  par par 0

                               TRACE PROPERTY  r(oprrpres)  w w 1

                               TRACE PROPERTY  r(oprrpres)  l l 1

                               TRACE PROPERTY  r(oprrpres)  sbar sbar 0

                               TRACE PROPERTY  r(oprrpres)  pbar pbar 0

                               TRACE PROPERTY  r(oprrpres)  bp bp 0

                               TRACE PROPERTY  r(oprrpres)  m m 0

                               TRACE PROPERTY  r(oprrpres)  par par 0

                               TRACE PROPERTY  r(opndres)  w w 1

                               TRACE PROPERTY  r(opndres)  l l 1

                               TRACE PROPERTY  r(opndres)  sbar sbar 0

                               TRACE PROPERTY  r(opndres)  pbar pbar 0

                               TRACE PROPERTY  r(opndres)  m m 0

                               TRACE PROPERTY  r(opndres)  par par 0

                               TRACE PROPERTY  r(oppdres)  w w 1

                               TRACE PROPERTY  r(oppdres)  l l 1

                               TRACE PROPERTY  r(oppdres)  s s 0

                               TRACE PROPERTY  r(oppdres)  pbar pbar 0

                               TRACE PROPERTY  r(oppdres)  m m 0

                               TRACE PROPERTY  r(oppdres)  par par 0

                               TRACE PROPERTY  r(sblkndres)  w w 1

                               TRACE PROPERTY  r(sblkndres)  l l 1

                               TRACE PROPERTY  r(sblkndres)  sbar sbar 0

                               TRACE PROPERTY  r(sblkpdres)  w w 1

                               TRACE PROPERTY  r(sblkpdres)  l l 1

                               TRACE PROPERTY  r(sblkpdres)  s s 0

                               TRACE PROPERTY  r(sblkpdres)  pbar pbar 0

                               TRACE PROPERTY  r(kqres)  w w 1

                               TRACE PROPERTY  r(kqres)  l l 1

                               TRACE PROPERTY  r(kqres)  sbar sbar 0

                               TRACE PROPERTY  r(kqres)  pbar pbar 0

                               TRACE PROPERTY  r(kqres)  bp bp 0

                               TRACE PROPERTY  r(kqres)  m m 0

                               TRACE PROPERTY  r(kqres)  par par 0

                               TRACE PROPERTY  r(nsres)  w w 1

                               TRACE PROPERTY  r(nsres)  l l 1

                               TRACE PROPERTY  r(nsres)  sbar sbar 0

                               TRACE PROPERTY  r(nsres)  pbar pbar 0

                               TRACE PROPERTY  r(nsres)  m m 0

                               TRACE PROPERTY  r(nsres)  par par 0

                               TRACE PROPERTY  d(sbd)  l l 1

                               TRACE PROPERTY  d(sbd)  w w 1

                               TRACE PROPERTY  d(sbd)  nf nf 0

                               TRACE PROPERTY  d(sbd)  m m 0

                               TRACE PROPERTY  d(sbd)  par par 0

                               TRACE PROPERTY  d(var)  l l 1

                               TRACE PROPERTY  d(var)  w w 1

                               TRACE PROPERTY  d(var)  nf nf 0

                               TRACE PROPERTY  d(dipdnw)  w w 1

                               TRACE PROPERTY  d(dipdnw)  l l 1

                               TRACE PROPERTY  d(dipdnw)  nf nf 0

                               TRACE PROPERTY  d(pin)  l l 1e-08 ABSOLUTE

                               TRACE PROPERTY  d(pin)  w w 1e-08 ABSOLUTE

                               TRACE PROPERTY  d(pin)  nf nf 0

                               TRACE PROPERTY  d(pin)  m m 0

                               TRACE PROPERTY  d(pin)  wca wca 0

                               TRACE PROPERTY  d(pin)  mswitch mswitch 0

                               TRACE PROPERTY  esdnsh_base  wesd wesd 1

                               TRACE PROPERTY  esdnsh_base  l l 1

                               TRACE PROPERTY  esdnsh_base  w w 1

                               TRACE PROPERTY  esdnsh_base  ldop ldop 1

                               TRACE PROPERTY  esdnsh_base  lsop lsop 1

                               TRACE PROPERTY  esdnsh_base  fetvoltage fetvoltage 0

                               TRACE PROPERTY  esdnsh_base  gns gns 0

                               TRACE PROPERTY  q(esdvpnp)  areae areae 1

                               TRACE PROPERTY  q(esdvpnp)  areab areab 1

                               TRACE PROPERTY  q(esdvpnp)  pjerx pjerx 1

                               TRACE PROPERTY  q(esdvpnp)  pjb pjb 1

                               TRACE PROPERTY  q(esdvpnp)  nf nf 0

                               TRACE PROPERTY  esdvpnp_t3  areae areae 1

                               TRACE PROPERTY  esdvpnp_t3  areab areab 1

                               TRACE PROPERTY  esdvpnp_t3  pjerx pjerx 1

                               TRACE PROPERTY  esdvpnp_t3  pjb pjb 1

                               TRACE PROPERTY  esdvpnp_t3  nf nf 0

                               TRACE PROPERTY  esdvnpn  areac areac 1

                               TRACE PROPERTY  esdvnpn  pjc pjc 1

                               TRACE PROPERTY  esdvnpn  nf nf 0

                               TRACE PROPERTY  d(esdndsx)  areac areac 1

                               TRACE PROPERTY  d(esdndsx)  pjc pjc 1

                               TRACE PROPERTY  d(esdndsx)  nf nf 0

                               TRACE PROPERTY  d(esdnwsx)  perim perim 1

                               TRACE PROPERTY  d(esdnwsx)  nf nf 0

                               TRACE PROPERTY  d(esdnwsx)  bp bp 0

                               TRACE PROPERTY  d(esdpnpi)  a a 1

                               TRACE PROPERTY  d(esdpnpi)  perim perim 1

                               TRACE PROPERTY  d(esdpnpi)  nanod nanod 0

                               TRACE PROPERTY  d(esdndpi)  a a 1

                               TRACE PROPERTY  d(esdndpi)  perim perim 1

                               TRACE PROPERTY  d(esdndpi)  ncath ncath 0

                               TRACE PROPERTY  c(mim)  w w 1

                               TRACE PROPERTY  c(mim)  l l 1

                               TRACE PROPERTY  c(mim)  bp bp 0

                               TRACE PROPERTY  c(mim)  m m 0

                               TRACE PROPERTY  c(mim)  par par 0

                               TRACE PROPERTY  c(dualmim)  w w 1

                               TRACE PROPERTY  c(dualmim)  l l 1

                               TRACE PROPERTY  c(dualmim)  bp bp 0

                               TRACE PROPERTY  c(dualmim)  qycon qycon 0

                               TRACE PROPERTY  c(dualmim)  m m 0

                               TRACE PROPERTY  c(dualmim)  par par 0

                               TRACE PROPERTY  d(havar)  w w 0.1

                               TRACE PROPERTY  d(havar)  l l 0.1

                               TRACE PROPERTY  d(havar)  nf nf 0

                               TRACE PROPERTY  d(havar)  m m 0

                               TRACE PROPERTY  d(havar)  mswitch mswitch 0

                               TRACE PROPERTY  diffhavar  w w 0.1

                               TRACE PROPERTY  diffhavar  l l 0.1

                               TRACE PROPERTY  diffhavar  nf nf 0

                               TRACE PROPERTY  diffhavar  m m 0

                               TRACE PROPERTY  diffncap  w w 1

                               TRACE PROPERTY  diffncap  l l 1

                               TRACE PROPERTY  diffncap  nf nf 0

                               TRACE PROPERTY  diffncap  m m 0

                               TRACE PROPERTY  q(divpnp)  w w 0.1

                               TRACE PROPERTY  q(divpnp)  l l 0.1

                               TRACE PROPERTY  q(divpnp)  nf nf 0

                               TRACE PROPERTY  q(divpnp)  m m 0

                               TRACE PROPERTY  q(divpnp)  par par 0

                               TRACE PROPERTY  q(divpnp)  mswitch mswitch 0

                               TRACE PROPERTY  bondpad  l l 1

                               TRACE PROPERTY  bondpad  w w 1

                               TRACE PROPERTY  bondpad  bp bp 0

                               TRACE PROPERTY  bondpad  rect rect 0

                               TRACE PROPERTY  bondpad  wbc4 wbc4 0

                               TRACE PROPERTY  q(npn)  exl exl 1

                               TRACE PROPERTY  q(npn)  exw exw 1

                               TRACE PROPERTY  q(npn)  hb hb 0

                               TRACE PROPERTY  q(npn)  mult mult 0

                               TRACE PROPERTY  q(npn)  topo topo 0

                               TRACE PROPERTY  q(npn)  nstripes nstripes 0

                               TRACE PROPERTY  q(npn)  rel rel 0

                               TRACE PROPERTY  q(npn)  mswitch mswitch 0

                               TRACE PROPERTY  npnt  exl exl 1

                               TRACE PROPERTY  npnt  exw exw 1

                               TRACE PROPERTY  npnt  hb hb 0

                               TRACE PROPERTY  npnt  mult mult 0

                               TRACE PROPERTY  npnt  topo topo 0

                               TRACE PROPERTY  npnt  nstripes nstripes 0

                               TRACE PROPERTY  npnt  rel rel 0

                               TRACE PROPERTY  npnt  mswitch mswitch 0

                               TRACE PROPERTY  q(npnxp)  exl exl 1

                               TRACE PROPERTY  q(npnxp)  exw exw 1

                               TRACE PROPERTY  q(npnxp)  hb hb 0

                               TRACE PROPERTY  q(npnxp)  mult mult 0

                               TRACE PROPERTY  q(npnxp)  topo topo 0

                               TRACE PROPERTY  q(npnxp)  nstripes nstripes 0

                               TRACE PROPERTY  q(npnxp)  rel rel 0

                               TRACE PROPERTY  q(npnxp)  mswitch mswitch 0

                               TRACE PROPERTY  npnxpt  exl exl 1

                               TRACE PROPERTY  npnxpt  exw exw 1

                               TRACE PROPERTY  npnxpt  hb hb 0

                               TRACE PROPERTY  npnxpt  mult mult 0

                               TRACE PROPERTY  npnxpt  topo topo 0

                               TRACE PROPERTY  npnxpt  nstripes nstripes 0

                               TRACE PROPERTY  npnxpt  rel rel 0

                               TRACE PROPERTY  npnxpt  mswitch mswitch 0

                               TRACE PROPERTY  ind  x x 1

                               TRACE PROPERTY  ind  s s 1

                               TRACE PROPERTY  ind  w w 1e-08 ABSOLUTE

                               TRACE PROPERTY  ind  wu wu 1e-08 ABSOLUTE

                               TRACE PROPERTY  ind  n n 0

                               TRACE PROPERTY  ind  bp bp 0

                               TRACE PROPERTY  indp  x x 1

                               TRACE PROPERTY  indp  s s 1

                               TRACE PROPERTY  indp  w w 1

                               TRACE PROPERTY  indp  wu wu 1

                               TRACE PROPERTY  indp  n n 0

                               TRACE PROPERTY  indp  bp bp 0

                               TRACE PROPERTY  inds  x x 2

                               TRACE PROPERTY  inds  s s 1

                               TRACE PROPERTY  inds  w w 1

                               TRACE PROPERTY  inds  n n 0

                               TRACE PROPERTY  inds  bp bp 0

                               TRACE PROPERTY  symindp  s s 1

                               TRACE PROPERTY  symindp  w w 1

                               TRACE PROPERTY  symindp  wu wu 1

                               TRACE PROPERTY  symindp  n n 0

                               TRACE PROPERTY  symindp  bp bp 0

                               TRACE PROPERTY  symindp  x x 0

                               TRACE PROPERTY  symind  s s 1

                               TRACE PROPERTY  symind  w w 1

                               TRACE PROPERTY  symind  wu wu 1

                               TRACE PROPERTY  symind  n n 0

                               TRACE PROPERTY  symind  bp bp 0

                               TRACE PROPERTY  symind  x x 0

                               TRACE PROPERTY  coupledcpw  w w 0

                               TRACE PROPERTY  coupledcpw  l l 0

                               TRACE PROPERTY  coupledcpw  s s 0

                               TRACE PROPERTY  coupledcpw  d d 0

                               TRACE PROPERTY  coupledcpw  layer_sig layer_sig 0

                               TRACE PROPERTY  singlecpw  w w 0

                               TRACE PROPERTY  singlecpw  l l 0

                               TRACE PROPERTY  singlecpw  s s 0

                               TRACE PROPERTY  singlecpw  layer_sig layer_sig 0

                               TRACE PROPERTY  coupledwires  w w 0

                               TRACE PROPERTY  coupledwires  l l 0

                               TRACE PROPERTY  coupledwires  s s 0

                               TRACE PROPERTY  coupledwires  d d 0

                               TRACE PROPERTY  coupledwires  shieldsads shieldsads 0

                               TRACE PROPERTY  coupledwires  layerads layerads 0

                               TRACE PROPERTY  coupledwires  overads overads 0

                               TRACE PROPERTY  singlewire  w w 0

                               TRACE PROPERTY  singlewire  l l 1e-08 ABSOLUTE

                               TRACE PROPERTY  singlewire  s s 0

                               TRACE PROPERTY  singlewire  shieldsads shieldsads 0

                               TRACE PROPERTY  singlewire  layerads layerads 0

                               TRACE PROPERTY  singlewire  overads overads 0

                               TRACE PROPERTY  rfline  w w 2

                               TRACE PROPERTY  rfline  l l 2

                               TRACE PROPERTY  vpnpsx  nstripes nstripes 0

                               TRACE PROPERTY  vpnpsx  evl evl 1

                               TRACE PROPERTY  vpnpsx  evw evw 1

                               TRACE PROPERTY  vpnpsx  par par 0

                               TRACE PROPERTY  vpnpsx  ccr ccr 0

                               TRACE PROPERTY  vpnpsx  pbm1 pbm1 0

                               TRACE PROPERTY  tsv2  slots slots 0

                               TRACE PROPERTY  tsv2  nrows nrows 0

                               TRACE PROPERTY  bend  l l 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  bend  w w 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  bend  s s 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  bend  layerads layerads 0.01

                               TRACE PROPERTY  bend  overads overads 0.01

                               TRACE PROPERTY  bend  shieldsads shieldsads 0.01

                               TRACE PROPERTY  bend  miter miter 0.01

                               TRACE PROPERTY  step  l l 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  step  w1 w1 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  step  w2 w2 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  step  s s 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  step  layerads layerads 0.01

                               TRACE PROPERTY  step  overads overads 0.01

                               TRACE PROPERTY  step  shieldsads shieldsads 0.01

                               TRACE PROPERTY  tee  w1 w1 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  tee  w2 w2 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  tee  w3 w3 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  tee  l1 l1 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  tee  l2 l2 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  tee  l3 l3 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  tee  s s 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  tee  layerads layerads 0.01

                               TRACE PROPERTY  tee  overads overads 0.01

                               TRACE PROPERTY  tee  shieldsads shieldsads 0.01

                               TRACE PROPERTY  open  l l 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  open  w w 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  open  s s 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  open  layerads layerads 0.01

                               TRACE PROPERTY  open  overads overads 0.01

                               TRACE PROPERTY  open  shieldsads shieldsads 0.01

                               TRACE PROPERTY  short  l l 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  short  w w 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  short  s s 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  short  layerads layerads 0.01

                               TRACE PROPERTY  short  overads overads 0.01

                               TRACE PROPERTY  short  shieldsads shieldsads 0.01

                               TRACE PROPERTY  gap  l l 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  gap  gapd gapd 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  gap  w1 w1 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  gap  w2 w2 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  gap  s s 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  gap  layerads layerads 0.01

                               TRACE PROPERTY  gap  overads overads 0.01

                               TRACE PROPERTY  gap  shieldsads shieldsads 0.01

                               TRACE PROPERTY  taper  ltaper ltaper 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  taper  w1 w1 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  taper  w2 w2 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  taper  s s 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  taper  layerads layerads 0.01

                               TRACE PROPERTY  taper  overads overads 0.01

                               TRACE PROPERTY  taper  shieldsads shieldsads 0.01

                               TRACE PROPERTY  radialstub  stubw stubw 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  radialstub  stubl stubl 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  radialstub  layerads layerads 0.01

                               TRACE PROPERTY  radialstub  overads overads 0.01

                               TRACE PROPERTY  radialstub  angle angle 0.01

                               TRACE PROPERTY  yjunction  w1 w1 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  yjunction  w2 w2 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  yjunction  sep sep 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  yjunction  s s 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  yjunction  layerads layerads 0.01

                               TRACE PROPERTY  yjunction  overads overads 0.01

                               TRACE PROPERTY  yjunction  shieldsads shieldsads 0.01

                               TRACE PROPERTY  langecoupler  w w 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  langecoupler  wf wf 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  langecoupler  l l 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  langecoupler  s s 2.5e-09 ABSOLUTE

                               TRACE PROPERTY  langecoupler  layerads layerads 0.01

                               TRACE PROPERTY  langecoupler  overads overads 0.01

                             

                             

                               // User Trace Property

                             

                             

                               TRACE PROPERTY  ncap  nf nrep m l w

                               TRACE PROPERTY  dgncap  nf nrep m l w

                             

                             

                             

                             

                             

                             

                                               CELL COMPARISON RESULTS ( TOP LEVEL )

                             

                             

                             

                             

                             

                             

                                              #   #         ##################### 

                                               # #          #                   # 

                                                #           #     INCORRECT     # 

                                               # #          #                   # 

                                              #   #         ##################### 

                             

                             

                             

                             

                              Error:    Different numbers of instances (see below).

                             

                             

                            LAYOUT CELL NAME:         ind_bal_100p

                            SOURCE CELL NAME:         ind_bal_100p

                             

                             

                            --------------------------------------------------------------------------------------------------------------

                             

                             

                            INITIAL NUMBERS OF OBJECTS

                            --------------------------

                             

                             

                                            Layout    Source         Component Type

                                            ------    ------         --------------

                            Ports:              4         5    *

                             

                             

                            Nets:               6         5    *

                             

                             

                            Instances:          0         2    *    R (2 pins): (p n)

                                                 4         0    *    R (2 pins): (p n)

                                            ------    ------

                            Total Inst:         4         2

                             

                             

                             

                             

                            NUMBERS OF OBJECTS AFTER TRANSFORMATION

                            ---------------------------------------

                             

                             

                                            Layout    Source         Component Type

                                            ------    ------         --------------

                            Ports:              4         4

                             

                             

                            Nets:               4         4

                             

                             

                            Instances:          0         2    *    R (2 pins): (p n)

                                            ------    ------

                            Total Inst:         0         2

                             

                             

                             

                             

                                   * = Number of objects in layout different from number in source.

                             

                             

                             

                             

                             

                             

                            **************************************************************************************************************

                                                             INCORRECT OBJECTS

                            **************************************************************************************************************

                             

                             

                             

                             

                            LEGEND:

                            -------

                             

                             

                              ne  = Naming Error (same layout name found in source

                                    circuit, but object was matched otherwise).

                             

                             

                             

                             

                            **************************************************************************************************************

                                                             INCORRECT INSTANCES

                             

                             

                            DISC#  LAYOUT NAME                                               SOURCE NAME

                            **************************************************************************************************************

                             

                             

                              1    ** missing instance **                                    RR1  R(lvsres)

                             

                             

                            --------------------------------------------------------------------------------------------------------------

                             

                             

                              2    ** missing instance **                                    RR0  R(lvsres)

                             

                             

                             

                             

                             

                             

                            **************************************************************************************************************

                                                           INFORMATION AND WARNINGS

                            **************************************************************************************************************

                             

                             

                             

                             

                                              Matched    Matched    Unmatched    Unmatched    Component

                                               Layout     Source       Layout       Source    Type

                                              -------    -------    ---------    ---------    ---------

                               Ports:               4          4            0            0

                             

                             

                               Nets:                4          4            0            0

                             

                             

                               Instances:           0          0            0            2    R(lvsres)

                                              -------    -------    ---------    ---------

                               Total Inst:          0          0            0            2

                             

                             

                             

                             

                            o Statistics:

                             

                             

                               2 passthrough layout nets were found.

                               1 passthrough source net was deleted.

                             

                             

                               4 unused layout resistors were deleted.

                             

                             

                               2 layout nets had all their pins removed and were deleted.

                             

                             

                               2 layout nets were reduced to passthrough nets.

                             

                             

                             

                             

                            o Passthrough Layout Nets And Their Ports:

                             

                             

                                  (Layout nets which are connected only to ports).

                             

                             

                               P3 (port: P3), P1 (port: P1),

                             

                             

                             

                             

                            o Initial Correspondence Points:

                             

                             

                               Ports:        P1 P4 P2 P3

                             

                             

                             

                             

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                                                                     SUMMARY

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                            • 11. Re: LVS BOX does not bypass subckt for custom cell
                              dan_liddell

                              Per the first warning in the LVS report, the subcircuit ind_bal_100p is declared more than once in the source netlist (due to the .include we discussed earlier, it appears). Which of the duplicate instances is actually used during LVS is arbitrary. If all instances are identical, then your LVS results are reliable, but it is still a good practice to remove the redundancy.

                               

                              Before circuit transformation occurs, the source has two resistors and the layout has four. But after transformation, the layout has none. In the information and warnings section of the LVS report, there is this:

                               

                              4 unused layout resistors were deleted.

                               

                              Which is related to this rule file setting:

                               

                              LVS Filter Unused Option RC

                               

                              If you disable that setting and enable LVS Report Option FX, you'll get a detailed report that gives suggestions for how to fix the problem.

                               

                              Looking at the layout netlist that you showed earlier, we have this:

                               

                              <see linked file below or refer to layout netlist shown earlier>

                               

                              Each of these R devices has its pins shorted together. Hence, LVS Filter Unused Option RC would cause them to be filtered out during comparison. But the source doesn't have its resistor pins shorted together. If this is an accurate representation of your current layout, the connectivity of the resistor pins requires attention.

                               

                              Assuming parallel R reduction is on, this connectivity would suffice before circuit transformation:

                               

                              .SUB ind_bal_100p P1 P4 P2 P3

                              R0 P1 P2 …

                              R1 P1 P2 …

                              R3 P3 P4 …

                              R4 P3 P4 …

                              .ENDS

                               

                              R0 and R1 would then be reduced together and the same holds for R3 and R4. (Currently, the resistor property values do not match between layout and source before or after parallel reduction, so if you trace resistance for those resistors, there will be an R property discrepancy.)

                               

                              It is important that connectivity not be shorted through these R device bodies, so care must be taken in deriving the layers used in the Device statements for Device templates $D = 364 and 365.

                               

                              Hope that helps.

                               

                              dan