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LVS BOX does not bypass subckt for custom cell

Question asked by rcy22 on Dec 18, 2018
Latest reply on Jan 4, 2019 by dan_liddell

To whom it may concern,

 

I have designed my own inductor using EMX with ports and an extracted DC model of a resistor between the IN and OUT ports of the inductor.

 

My process includes a RES layer which isolates the IN and OUT of otherwise shorted strip of metal. However, when I run LVS with the LVS BOX function for SOURCE and LAYOUT I still get a warning box that states:
"source netlist references but does not define 1 subckt: ind_bal_100p"

 

 

My understanding from reading the SVRF documentation from MentorGraphics PDK was that the LVS BOX command would cause LVS to not look for the ind_bal_100p netlist. Am I missing something?

 

thank you

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