AnsweredAssumed Answered

instantiation input value

Question asked by daviddadush on Jan 2, 2019
Latest reply on Jan 2, 2019 by lane_scheideman

hi everyone
i need some help to understand some problem, the compiler don't refer to the value in the parentheses.

 

i.e:
"xxxxx"  module name
(

clock  ( any input ),

...

...

)

 

for "any input" that i write in the parentheses the compiler will ignore the value of the value even if i write there parameter that don't declare before the compiler will ignore it.

 

(i know that I'm compiling the right file because if i write something out side the parentheses  the compilation will fail)

 

i use questaSim and write with Systemverilog

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