2 Replies Latest reply on Jan 2, 2019 10:23 AM by lane_scheideman

    instantiation input value

    daviddadush

      hi everyone
      i need some help to understand some problem, the compiler don't refer to the value in the parentheses.

       

      i.e:
      "xxxxx"  module name
      (

      clock  ( any input ),

      ...

      ...

      )

       

      for "any input" that i write in the parentheses the compiler will ignore the value of the value even if i write there parameter that don't declare before the compiler will ignore it.

       

      (i know that I'm compiling the right file because if i write something out side the parentheses  the compilation will fail)

       

      i use questaSim and write with Systemverilog