On a DDR4 interface we are trying to do delay matching in layout (VX 2.4). This is done using CES, however CES is giving us violations which we don't really have a clue yet on why we get these violations. In order to debug, i'm trying to check the delay matching in Hyperlynx DRC. In CES the pin package length of our IC pins have been filled in. However if I import the design in DRC then the pin package length and corresponding delays are not filled in. Is there an easy way to import these pin package lengths?
I have them in CES and in an excel seperately but the only way i'm able to do it right now is to manually fill in the pin package lengths in DRC.