I am using hyperlynx for post route analysis on a DDR4 interface. I am trying to understand the ODT model selection for the controller and memory. I believe the ODT disabled column is for reads while the ODT enabled column is for writes. This makes sense as the memory would enable ODT for writes and disables ODT for reads. My question pertains to the DM signals.
The controller is pre-populated for ODT disabled and ODT Enabled. What is the typical reason for this?
Also, on the memory side (of which I am using a micron part), would the ODT selection be similar to the DQS and DQ? Or similar to the controller?