3 Replies Latest reply on Mar 6, 2019 2:40 AM by weston_beal

    Understanding difference between lumped and distributed decoupling analysis with simple R-L-C or S-parameter model

    hungdang1506

      Dear Experts,

      I try to simulate PDN by lumped and distributed analysis with simple RLC and S-parameter model for the capacitor.

      Please see the result in the picture below:

       

      my Ztarget = 0.93 * 0.05 / (0.5 * 154) = 0.6mOhm.

      Look into the result, I have some concerns below:

      1 /. Why is there a big gap between blue line and red line? It mean which is more accuracy? simple RLC or S-parameter / SPICE model?

      2 /. To tune PDN by changing the decoupling capacitor, which method simulation I should follow? Distributed or lumped analysis?

       

      Thank you so much.

       

      Ce message a été modifié par : Hung Dang

        • 1. Re: Understanding difference between lumped and distributed decoupling analysis with simple R-L-C or S-parameter model
          weston_beal

          To answer your questions:

          1 /. Why is there a big gap between the blue line and red line?

               because the lumped RLC model does not match the impedance of the S-parameter model.

          It mean which is more accurate?

               There is no way to know from this result. Accuracy depends on how well the model matches the real world. You have not shown the response of the real world.

          simple RLC or S-parameter / SPICE model?

          2 /. To tune PDN by changing the decoupling capacitor, which method simulation I should follow? Distributed or lumped analysis?

               The final analysis always needs to be distributed analysis. We use lumped analysis in the early stages of design because it runs much faster and is a good approximation.

           

           

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          • 2. Re: Understanding difference between lumped and distributed decoupling analysis with simple R-L-C or S-parameter model
            hungdang1506

            Dear Weston,

            Thank you for your answer.

            I have some items below need to discuss with you.

            1/. I always use S-parameter/SPICE model from vendor's website such as TDK, Murata, Yayeo...So I think these models will be more accurate than the simple R-L-C model.

            2/. I update PDN result after I used distributed analysis to tune the decoupling caps.

            My Ztarget is near 0.6mOhm. It is very difficult to meet Ztarget up to 20Mhz.

            As I know, VRM will handle up to 100khz, up to 100Mhz for board level and up to 1Ghz for Package.

            How to meet Ztarget up to 20Mhz for board level?

            How to simulate PDN for both VRM, board and package at the same time?

             

            Thank you so much.

            • 3. Re: Understanding difference between lumped and distributed decoupling analysis with simple R-L-C or S-parameter model
              weston_beal

              1. The advantage of an S-parameter model over a simple RLC model is that it can generally capture more effects (resonances) of the device geometry. The disadvantage is that the file can contain a lot of data and it might be difficult to determine if the data is correct. Assuming that both formats are accurate, I would use the S parameters in order to include more effects of the device. I would also carefully check the validity of the S parameters.

              https://support.mentor.com/en/knowledge-base/MG604887

               

              2. You should include the VRM model on the appropriate pin for the net you are simulating. The analysis is only at the PCB level for now; the package of the sink IC is not included. Therefore, we look at the impedance only up to the low-pass frequency of the package. You might need to estimate this frequency. I agree that 0.6mOhm target is quite difficult. As you can see, the impedance of the PDN is dominated by inductance above about 4MHz. You need to really concentrate on low-inductance connections and decoupling capacitor mounting. Use a thin dielectric between VDD and VSS planes. Mount capacitors on the side of the PCB closest to the plane pair. Place the capacitor vias as close as possible to the capacitor pins AND to each other. Place capacitors as close as possible to each IC power and ground pin pair.