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Issue with Clock / Address / Command Group in DDR3 Simulation

Question asked by mwill195 on Mar 5, 2019
Latest reply on Mar 5, 2019 by mwill195

I am currently using Hyperlynx Boardsim X.2.4 to simulate a DDR3 design with an iMX6 processor connected to two DDR3 ICs. The routing topology is with a single T branch for address control and clock. The differential clock lines have a termination resistor between them. The address/command have resistor termination to VTT at 0.75V.


When I run the simulation the data lines, strobes, mask (point to point) all look good. However the address/clock fails with bad signal - looking on the scope I can see why as the address lines barely swing 100mV either side of Vref and the clock (shown as AC) swings +/- 170mV.


Studying my setup I have:

  • Imported the hyp file from Altium
  • Assigned IBIS models to the iMX6 and DDR3 devices, assigned models to the termination resistors
  • Assigned voltage to the VTT and VREF nets. The termination resistors pull to Vref
  • I have not assigned models to any decoupling on VTT or the VTT regulator


The only potential issue I can see is that the T-branches are split at a "component" rather than a via. To perform length matching in Altium a "t point component" needed to be created which is essentially a single pad the same as a via. Altium can then give lengths on the trunk and branches of the tree whereas vias are transparent to these calcs.


The T-point has a ref des of "T" and the ref des mapping thinks these are an IC, albeit with no model. Will I need to assign a model to these points or will Hyperlynx see them as transparent / vias without the model?


I tried mapping T to type "connector" but after reloading the design it still wants T to be an IC in the model assignments window.


I would appreciate any advice on why my waveforms on these terminated lines are coming out like this and if it is due to the t-point component with type IC (no model assigned).


Thank you, Mark


Bad Address and Clock.png