3 Replies Latest reply on Mar 5, 2019 8:09 AM by mwill195

    Issue with Clock / Address / Command Group in DDR3 Simulation


      I am currently using Hyperlynx Boardsim X.2.4 to simulate a DDR3 design with an iMX6 processor connected to two DDR3 ICs. The routing topology is with a single T branch for address control and clock. The differential clock lines have a termination resistor between them. The address/command have resistor termination to VTT at 0.75V.


      When I run the simulation the data lines, strobes, mask (point to point) all look good. However the address/clock fails with bad signal - looking on the scope I can see why as the address lines barely swing 100mV either side of Vref and the clock (shown as AC) swings +/- 170mV.


      Studying my setup I have:

      • Imported the hyp file from Altium
      • Assigned IBIS models to the iMX6 and DDR3 devices, assigned models to the termination resistors
      • Assigned voltage to the VTT and VREF nets. The termination resistors pull to Vref
      • I have not assigned models to any decoupling on VTT or the VTT regulator


      The only potential issue I can see is that the T-branches are split at a "component" rather than a via. To perform length matching in Altium a "t point component" needed to be created which is essentially a single pad the same as a via. Altium can then give lengths on the trunk and branches of the tree whereas vias are transparent to these calcs.


      The T-point has a ref des of "T" and the ref des mapping thinks these are an IC, albeit with no model. Will I need to assign a model to these points or will Hyperlynx see them as transparent / vias without the model?


      I tried mapping T to type "connector" but after reloading the design it still wants T to be an IC in the model assignments window.


      I would appreciate any advice on why my waveforms on these terminated lines are coming out like this and if it is due to the t-point component with type IC (no model assigned).


      Thank you, Mark


      Bad Address and Clock.png

        • 1. Re: Issue with Clock / Address / Command Group in DDR3 Simulation

          Ok I think I found my issue! Going through the setup carefully I noticed in the DDR wizard that the non-ODT address/command/clock signals were using a model with 240R source termination. Changing to 40R produces a pass on all waveforms and the signal amplitudes naturally look a lot better.


          However I would still like to just verify that the t-point components are ok with just being left without a model? Ideally they would use a via model so any parasitics are taken into account. Is this possible to assign to these parts?



          • 2. Re: Issue with Clock / Address / Command Group in DDR3 Simulation



            Normally, HyperLynx SI removes one-pin components when it loads the design. Check that you didn't bypass this step when first loading the design. Also, there is an option to treat test-points as IC pins. Check that this option is not enabled.


            Then, when you use the reference designator mapping, you probably want to map T to Test point rather than connector.


            Still, if the T-point pin does not have a model assigned then it is effectively open. The DDR wizard will probably issue a warning about all these unassigned pins every time you run it. If you want to see how the via is models, you can export one of the nets to LineSim and see if the via is included in the exported net.

            • 3. Re: Issue with Clock / Address / Command Group in DDR3 Simulation

              Hi Weston,


              Thank you for your reply. The simulation seems to run ok producing signals at each DRAM - I guess as this is a one-pin component it can be "open" but there isn't a second terminal for it to be open with respect to. The geometry of the T-point is exactly the same as my vias.


              I am still unsure of how these are being modelled when I run my simulation - I don't want any false positives because the effects of the layer transition is being ignored at this point. They are essentially down as IC without a model. But they link the signal between layers and hyperlynx must be taking this into account in some way for my signal to reach the DRAM, otherwise it would stop at the T-point.


              If you have a signal that uses a through-hole component pin to change layer rather than an actual via does the software still take any parasitics of this into account?


              I guess for simulation, now I have achieved my length matching I could replace all of these T-points with vias and re-export the design from Altium so hyperlynx treats the point as an actual via.


              Thank you for your help, Mark