I've been using a demo of DFT Audit as we need to implement full net functional testing to our PCB's on the bottom side only, as the DFT Audit setup requires via's to be used instead of dedicated components for testpoints this does not appear to allow any backwards annotation to the schematic once these are placed on the net in the PCB design?.
To get round this we have created a dedicated component pad and added these on the schematic on each net and passed these through to the PCB layout, these were then designated as testpoints to allow DFT audit to then produce the desired report to see if any nets had been missed.
I also again tried this on DFT Audit using pads router to autoplace these after setting up the appropriate criteria by setting up a bottom side biased via with no holes for the testpoints
this gave varied results and even placed testpoints under a component in one instance (see attachment) the component in question was placed on a 45° angle for (space saving) but it appears the via placement routine did not detect the placement outline? there are also discrepancies with the clearances specified in the properties tab as these are measured from the edge of the testpoint, the nailsize diameter (fixture drill sizes) shown also give the wrong spacing when checking these using the DRC on testpoints within Pads and give errors as a result?.
Has anyone else got any experience in using DFT audit they can see an easier way to implement this.