3 Replies Latest reply on Apr 11, 2019 8:52 AM by weston_beal

    error while simulating PCIe signals

    judson_antu

      Hi,

           I am trying to simulate eye diagram for  PCIe(gen2), between 2 FPGA's(XC7K410T-2FBG900C) on separate boards. There is a driver(DS80PCI402SQ/NOPB) on one board for the PCIe signals. Once the simulation reaches 100%, a report is generated with the following errors/warnings.(attached screenshot of the report as "report.PNG")

      ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------

         Messages from AMI models:

      I:    AMI_Init of Rx [ U2.2p (at die)/U2.2n (at die) ] returned:

             *** Xilinx 7 Series GTX Rx model ***

             

      W: Warning building plots for probe U2.2p (at die)/U2.2n (at die):

         Time=2.57923e-005: clock generated by the Rx AMI model looks unrealistic; this may result in eye closure

          

         The problem above could be due to a failure in the AMI model’s code (e.g., data-rate limitation, unsupported # of samples per bit, etc.); or could indicate the actual Rx behavior under the simulation conditions. Try modifying the AMI model’s settings and/or simulation stimulus first; if failures still occur, contact the silicon vendor for detailed support for the AMI model.

          

         Time=2.57923e-005: clock generated by the Rx AMI model looks unrealistic; this may result in eye closure

        Time=2.87043e-005: clock generated by the Rx AMI model looks unrealistic; this may result in eye closure

        Time=2.91443e-005: clock generated by the Rx AMI model looks unrealistic; this may result in eye closure

      Time=2.99003e-005: clock generated by the Rx AMI model looks unrealistic; this may result in eye closure

      Further warnings of this type suppressed

      -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

      in the error they mentioned "Try modifying the AMI model’s settings and/or simulation stimulus first" but I'm not sure which are the settings that need to be modified.

      I have attached the following photos for reference.

       

      eye diagram

      linesim

      settings while running IBIS-AMI channel analysis.

      IBIS model of the driver

       

      Strange thing is that, while i simulated it without using the driver, i was able to get a pretty good eye. Please do point me in some direction

      I will be happy to provide further informations if required.

        • 1. Re: error while simulating PCIe signals
          weston_beal

          Judson,

           

          First, I would recommend creating a small, simple test case to see how the IBIS-AMI models work. When that works then you can add more complex interconnect elements to it.

           

          The AMI settings are in the IBIS-AMI Channel Analyzer on the page titled Configure AMI Models. Click the button Configure Tx AMI ... or Configure Rx AMI ... These open dialogs with settings specific parameters for the Tx and Rx AMI executable models.

           

          The stimulus settings are configured on the page titled Define AMI Stimulus. In the Advanced frame, uncheck the Default checkbox and try adjusting the options available there, specifically the samples per bit parameter. Some models expect a certain samples-per-bit value. Check the model documentation or the vendor support to get these expected values.

           

          I hope this helps.

           

          Weston

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          • 2. Re: error while simulating PCIe signals
            judson_antu

            hi,

                 Thank you for your suggestion Weston. As per your 1st recommendation, I split up the circuit into two. One, from FPGA to the PCIe driver and the other from the driver to the 2nd FPGA. Simulating those separately, I was able to get a successful eye pattern in each case. It only doesn't work, if both the parts are combined. (here I use the IC component symbol for the PCIE driver, instead of the differential IC symbol in the 2 part method)

            I hope that what I have obtained is the intended output.

             

            Thankyou

            • 3. Re: error while simulating PCIe signals
              weston_beal

              Judson,

               

              I'm not sure about your model configuration because I don't have the actual FFS file. It appears that you expect a signal to pass through U1, but I don't think that happens. If the model you have assigned to U1 is a standard IBIS component, there is no signal passed from the input pins to the output pins. If my assumption about your model is correct then it makes sense that you would get correct simulation results for the 2 sections of your schematic but not from end to end of the schematic.

               

              Regards,

              Weston