For some reasons, I am not able to import the Quartus Prime .qsys file to the HDL Designer. In attempts to find the cause, I tried a few various projects - from quite complex hierarchical ones to very simple with one-two IP blocks in the system, with Verilog top-level module as a wrapper around Qsys-generated IP and with Qsys IP declared as a top-level. All attempts end with the error message from Quartus Import: "Cannot import <system>.qsys. Toplevel design is not found."
I would appreciate if someone can point me in the right direction for fixing/working around this issue.
Message was edited by: Igor Komir - fixing title