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how to make lvs clean with different voltage domain ?

Question asked by nhumaile on Apr 30, 2019
Latest reply on May 6, 2019 by dan_liddell

Hi All,

I have a circuit called top_cell which contain 2 other  sub-circuit A_cell and B_cell

inside of A_cell and B_cell the power is vdd! and vss!. At the top_cell level A_cell need to connect to vddl_lvt and vssd_lvt while B_cell need to connect to vddl_mvt and vssd_mvt.  Both B_cell and A_cell is provide by place and route innovus tool and innovus tool didn't give any input for power because it treat vdd! and vss! as a global power

How can I make lvs is clean top_cell ? the layout connect to actually vddl_lvt, vssd_lvt, vddl_mvt, and vssd_mvt correctly please help to let me know