I'm not an experienced user of Hyperlynx tools. We are currently designing a board embedding a Xilinx Zynq MPSoC device interfacing 4 Micron DDR4 components.
Xilinx provided us a Hyperlynx DRC timing report showing timing violations. We've been using Hyperlynx DDRx in order to validate our design and the tool does not raise any timing violation... I must add we followed step by step the tool wizard configuration advised by Xilinx.
1. Should we have a correlation between Hyp. DRC and DDRx (at least on timing analysis)?
2. In case we should have a correlation, any clue of what we might doing wrong?
3. We use burried vias, does the tool take this structure into account during its analysis?
Thanks for any help you could provided on this subject.