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schematic verification

Question asked by cgoldenbus on Jun 10, 2019

Good afternoon everyone.

I have a question on schematic verification and setting up the rules properly using the verifydefaults.ini

We've been rebuilding our library from scratch and trying to incorporate the correct pintypes so we can run an ERC against the schematic.

 

I thought this was a great idea but I'm running into some issues that even when reading the help files, I'm not sure I get.

 

DRC-202  open emitter not pulled down.

Well for this application the emitter is direct connect, it's acting as a sink to turn on an LED.

according to the help file 

 

"drc-202 has an option to allow you to specify the Pull-down net(s), such as: GND VSS VEE (one or more strings separated by a space)"  

Kind of confused as to where that belongs? in with the serial resistors?

 

Same issue with DRC-201  but what if I have two serial components before the supply net.. I have the LED Anode pulled to the rail and then the cathode through the resistor and then the same transistor as above.

LED and Resistors are all set as analog pins, the transistor is  base -analog, emitter -oem  and collector as ocl.

 

Thanks,

 

Carl

 

 

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