We have a design with DDR4 with address/command group splitting on 3 layers (L2, L3 and L14 on a 16 layers hdi PCB). We are ready to adjust the traces propagation delay within ±8ps.
I'm concerned about matching the signals on L14 vs L2 and L3 since there is a "long" L3-L14 burried via between them. My questionning is about the Xpedition TOF calculation when matching traces. Is the via delay considered into the TOF calculation? How is it calculated? Does it consider the via length? Does it build a via model with parasitic
capacitance? That capacitance is known to increase the via delay...
I saw in the via definition a place to enter the via delay. Should we modelized the delay into our vias with Hyperlynx and put the numbers there? Should we only include delay caused by parasitic capacitance or the total via delay, including via's length?
Thank you very much!