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DDR3 Timing Models

Question asked by igby on Jul 15, 2019
Latest reply on Jul 15, 2019 by weston_beal

I am simulating a DDR3L interface between a Xilinx XCKU085 and a Micron MT41K512M8DA. I do not have the timing model for the FPGA controller so I am using the generic ones that came with Hyperlynx. The design passed when using ddr3_ctl_ideal.v but failed sample and hold margins when ddr3_ctl.v was used.
Question: If the design passed using the ddr3_ctl_ideal.v model, is it still necessary to get it to pass ddr3_ctl.v?

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