I have been scratching my head for a couple days now... I set up the DDRx simulation based on my design (included IBIS models, created controller timing model, etc.) and most of the results from simulation make sense except for the case of a slow read. In the case of a slow read the simulation somehow finds the eye crossing as a point of sampling. I have retraced my steps thoroughly and can't come up with anything that would suggest this is operator error.
I have 8 independent dram's (no fly-by routing) and all settings apply to everyone in a similar fashion, 6 of the 8 chips have good margins but two of them fail due to the bad delays. I believe the following image and delay tables will provide more explanation. If anyone has a good idea as to why this is happening it would be greatly appreciated.