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How do I use a setup pattern when generating a test pattern in tessent.

Question asked by imc_user8 on Sep 1, 2019

I am designing a mixed signal SOC where the SMPS must be switched on before scan and MBIST. 

In my SOC simulation testcase I shift in a pattern to control the SMPS through JTAG. How do I add that pattern when generating ATPG pattern? Do I add in STIL or PDL files?


So far I am running the Tessent Flat and Hierarchical flow UsageExample and simulated correctly. Where can I get advanced examples which allow user control over the patterns? 


I noticed there is a PLL-based example, where can I find that? 


PLL example.