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TSMC 65nm PDK CRN65 with Calibre LVS/DRC/PEX

Question asked by growingmind on Sep 17, 2019

My main questions have to do with the differences between the flow of doing LVS/DRC/PEX for Analog Design (ie. opamp layout and other analog circuits) vs. the RFIC flows (LNA, Mixer etc) where the foundry modelled pcells and you have to mindful about Calibre double counting the pcells.

 

I was given the following instructions for Pre 2008 Mentor Calibre.

 

For PEX flow:

 

In the LVS rule file add the following statements:

SOURCE CASE YES

LVS COMPARE CASE NAMES

 

In the PEX rule file add the following statement:

PEX IDEAL XCELL YES

 

I have Mentor Calibre 2017.

 

Now I was told for my version of Calibre:

 

In LVS rule file add:


LAYOUT CELL LIST pcells “rf component here*” “rf component here*”
LAYOUT PRESERVE CELL LIST pcells

 

In PEX rule file add:

 

Use XCELL file, add -I option at end.

rf component here* rf component here -I
rf component here* rf component here -I

 

Where rf component here is the pcell that should not be double counted (if the rf model of an nmos or pmos)

 

I assume I am adding all the RF components, transistors, passives (caps) etc in the LVS rule file that I have in the foundry provided PEX XCELL file.

 

Are these modifications correct ?  Am I correct ?  What happened to the SOURCE CASE YES, LVS COMPARE CASE NAMES, PEX IDEAL XCELL YES statements in the newer versions of Calibre ?

 

What are they used for - these additional switches and lines in the rules file ? What is an XCELL ? What is an HCELL ?

 

Also, for Analog Design Flow - ie. not using PCELLS modelled by PDK - do these changes need to be added ?

 

Finally, what is the source added file ?

 

Thank you.

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