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Two questions about testing with HDL designer

Question asked by talnaim on Sep 26, 2019

Hello,

 

1. I have successfully created a test bench with HDL designer, and I use Modelsim to simulate. By pressing the Modelsim icon and selecting "through components" I can simulate my design.

My question is about changing small things about my test bench. If I for example change a bit of a signal (be it in the test bench code or one of my design blocks), is there a faster way to update my simulation other than pressing the icon mentioned above (in HDL designer) again and waiting for Modelsim to update?

 

2. My current design is synthesized using Precision. After that, my design is programmed into the FPGA using Quartus.

After finishing simulation I would like to test my design using Quartus signalTap, but I have two problems with that:

 

a. I can not see my state machine states, so I cannot know which state i'm in.

b. When trying to insert some nodes into SignalTap and then programming the FPGA I get an error saying some signals I inserted are missing source.

 

I assume both problems (a and b) can be solved by using some preserve attribute (as the Precision synthesizer is probably "killing" those signals), but how can I use this attribute if I'm using the graphical tool to create state machines?

If this isn't the solution, then what is?

 

Thank you!

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