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Hyperlynx : DRR3 Batch Simulation Data Read Problem

Question asked by m.ather on Oct 23, 2019
Latest reply on May 20, 2020 by ecs

We are simulation DDR3L in our design and we are trying to simulate our chips through Hyperlynx DDR3 batch simulation. We have used one slot dual ranked settings. After setting the parameters required for DDR3 batch simulation, when we run the simulation it does not show the results for data read operation. Why is that so ?

Here are the snapshots of thee settings and their results.

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