I am using Calibre for verification and I am new to Calibre. I am trying to run LVS for a chip layout. There are standard cells and IO pads in the design. I have given the Layout as gdsii and schematic as cdl. When I run the LVS I am getting a huge report file. This has all mismatches from design and from inside the standard cells and IO pads.
Is there a way to prevent Calibre from running the LVS checks inside the standard cells and the IO pads so that I can have a manageable report file so that I can debug the errors more easily?