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Need Help for ddr3 simulation at 1600 MT/s (ddr3_ctl.v)

Question asked by m.ather on Dec 18, 2019
Latest reply on Dec 18, 2019 by weston_beal

I am designing a custom board with T1042 processor and adding DDR3 memory with it. Now at PCB stage i need to do some simulations to see if my RAM is routed well or not. i have successfully simulated it on 1333MHZ but when i load timing model of 1600MHZ frequency, it fail all read results in DDR batch simulation. when is see the ddr3_ctl.v file, i see a note on 1600MHZ timings
"// notice speed grades out of order -----"


so, i want you to provide me the ddr3_ctl.v file that have verified timing paramenters and i could use in my simulation.