I am running the Hyperlynx DDR4 Wizard and on WRITE_FAST cycle, many signals fails due to SLEWRATE problem.
I see values between -0.01 to -1.4 at the MAX-SLEWRATE column (see attached print-screen).
When I select the link of any SLEWRATE failure the pop up window (see attached print screen) shows me a measurement between the clock and some point at the middle of the "0" level of this DQ signal.
I expected to see a measurement over the rise/ fall time of the DQ/ CLK signal, showing that the time between the DQ/ CLK Vil and Vih is too long (the rise/ fall time slope is too low)
I have attached a screen shoot of the pop up window, and a zoom I have made on the spot at this window pointed to by the Wizard .
Can you explain please why the Wizard points me to this spot when I open the SLEWRATE failure link?
Where and how can I see the part of the wave where the -1V/nS slope was measured?
How can I overcome this problem?
What can be the reason that DQn fails at SLEWRATE and DQm (m = n+1) which runs adjacent to DQn, exact same length and width and PCB path doesn't present any problem what so ever? or having my best MAX Slewrate at "merely" 3.5V/nS means that it is just random "luck" that the other portion of the DQ signals didn't fail as well for MAX Slewrate...?
Looking forward to hear from you