I have been performing PI simulation for my High power board. During PI, the connector through-hole pins are considered as vias and the result is shown as a failure. I have set the via current limit constraint as 1.5A as per my design limit. But the tool considers all the high current carrying through-hole pins as Vias and the current per via result fails.
Please help with the same. Can we set the tool to avoid the connector through holes in vias? Or can we set a different pass constraint for different vias?
Is there a way to set pass criteria based on vias and pads, and not based on nets.