v_jn_azjq8

Hyperlynx PI: Current density failure while using large pads

Discussion created by v_jn_azjq8 on Apr 13, 2020
Latest reply on May 4, 2020 by weston_beal

Hi

 

I am performing PI simulations for my high current board design. I have high current switches and MOSFETs in my design. Many of the components have big exposed pads as the power paths. 

 

My problem is that, when I assign those pins as either source or sink, the tool assumes only the centre of the pad as source or sink. As a result, my simulations fail in current density constraint. 

This is because all the current flows into or from the centre point of the pad causing the current density to peak at that point. Also, vias only at the centre of the pad are loaded and surrounding vias aren't used. But in actual case that won't be the scenario as the power flow will be distributed across the area of the pads.

 

Please help me with how can I avoid this situation and get the PI result pass for current density.  I need the current flow to be more like in the actual scene where the whole pad will be used to source or sink current rather than the centre of the pad.

 

Thanks

Vignesh

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