Hyperlynx SI/PI via barrel plating thickness

Discussion created by henryh on May 8, 2020

In Hyperlynx SI/PI, there is a global setting that specifies the via barrel plating thickness but this affects all padstacks.  Is it possible for Mentor to add functionality to allow the user to selectively modify plating thickness per padstack?  In order words, don’t make this setting a global setting.  In some case, the user requires different plating thickness for different vias, especially for microvias where they are normally fabricated closed.


Bright Idea submittal: