we are simulating DDR3, in the DDR3 Wizard setup i have an doubt in simulation option, in the section measurements location for DDR & Controller what has to be enable either die/pin.
The preferred measurement location is at the pin for both components. Often, this is not optimal, so we switch where needed. The JEDEC specification for DRAM defines the timing and signal quality metrics at the pins, so we really want to measure the simulated signals at the pins. This is usually feasible because the DRAM package pins are short and disrupt the signal only a little. The controller is usually a much larger component with much longer package pins. The long pins cause the signal at the pin to be significantly different than the signal at the die. The reflections from the die back to the pin cause enough noise in the signal to make it impractical to measure correctly. Therefore, we change the measurement location of the controller to the die so that we can measure a cleaner signal. This is often more useful to compare with the controller timing and signal quality metrics anyway. If the controller vendor gives you timing and SI requirements, they are often specified at the die. These are the reasons that the default settings for measurement location are die at the controller and pin at the DRAM.
Thanks for u r suggestion.
I tried , when i placed Die at controller & pin at DDR all signals are passing in all cases(typical, fast, slow) except in data read some signals are failing in fast and slow conditions & all signals passing in typical condition.
when i placed pin at controller & pin at DDR all signals are passing in all cases(typical, fast, slow)for Address, Data write, Differential, skew except in data read all signals are failing.
Suggest me which measurment location has to be considered.
I have small doubt in analysis report, whether the signals has to pass in all cases( Typical, Fast, Slow) / typical condition is ok.
Thanks in Advance
It is common to measure the signal at the controller die because the package creates significant ringback at the pin. This is why you have more conditions passing when the measurement location is die rather than pin. The die should be the IC buffer on the silicon. In the simulation, it depends on the IBIS model. The IBIS component has a pin list and a package model. The die location in this case is at the node between the buffer model and the package model. I would expect to be able to get passing result for all corners on all signals to consider the design complete. If there are failures, you should find if the failures are created by poor simulation setup, models, or the design.
And also may i know what is meant Die ?
Retrieving data ...