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Need help for SERDES Batch Simulation

Question asked by jjmoran on May 20, 2020
Latest reply on May 20, 2020 by jjmoran

Hi, I'm performing SERDES Batch Simulation to some nets of a board that are driven from a Mezzanine card to a Virtex FPGA.

The problem is that I only have IBIS-AMI model of the FPGA, but I'm missing connector model and Mezzanine PCB file.

How accurate will this SERDES compliance analysis be without the mentioned models and files for multiboard project? I just want to analyze the routing of these lines.

I have found that some nets are not passing the tests JCOM (204C), I suppose there is no way to individually analyze them without assigning a driver, right? I suppose the only way would be to export the line to board sim and create a driver manually in place of the connector. Is there any other way?


Thanks a lot in advance.