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How to add delay on DDR address / command when batch simulation

Question asked by okokjason on May 25, 2020
Latest reply on Jun 1, 2020 by weston_beal

How to add delay at address/cmd/Data/Strobe  when using the DDR batch Board sim simulation?

I only see the write leveling sheet where i could add the delay on DQ/DQS.

I would need to considerate the internal wire bonding delay of controller such as FPGA.