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Modelsim/Questasim unit delay simulation

Question asked by mxm89 on Jun 9, 2020

I would like to launch an unit delay RTL simulation using Questasim 10.1. I ve look how to compile the design and i see there is an option +delay_mode_unit for compiling verilog files. My design is vhdl. Is there an option for this kind of design?

Thanks in Advance

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