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Xilinx FPGA and DDR4 simulation is not working, Vih and Vil levels is not meeting desired range.

Question asked by ashwin9754 on Jun 25, 2020
Latest reply on Jul 28, 2020 by weston_beal

Hi All,

 

I am doing the simulation for the xilinx FPGA and DDR4 interface. I have a proper eye opening but its referenced to 0V. The Eye starts from 0V to 0.6V, with the crossing point 0.3V. Any changes on driver/Receiver side need to be done? Please let me know. #Hyperlynx ddr4 simulation

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