LVS reports the different number of ports, even though IC compiler (Synopsys ICC) auto-floorplaned, auto-placed ports, and auto-placed the standard cells. The netlist that is extracted from GDSII file losing some ports. I checked my PnR design, several ports on the same metal layer (i.e., M2) have the same property. But some of them are not recognized by Calibre LVS. I already used map_layer during streaming out the GDS file.