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Undefine module issue in Gatelevel design flow

Question asked by n_pham_dacxw on Jul 31, 2020



I have a problem when using the Gate level design flow with tessent.



+ My flow is below:

set_context dft -no_rtl

read_liberty standard_cell.lib

read_liberty macro1.lib


read_verilog  top.v

read_core_description mem1.memlib

set_current_design top


+ The undefine modules happened below for standard cell.

520 // Design elaboration successful.
521 // Warning: Undefined modules were found.
522 // Before using "set_system_mode" or "create_flat_model", you must either define
523 // the missing modules using "read_verilog" and/or "read_cell_library", or use the
524 // following command to treat them as black boxes:
525 add_black_boxes -modules { \


My question: 

- Can we read the .lib library for standardcell and other technology cells using read_liberty ? 

- What can be a problem for this missing module ?