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AC Decoupling Analysis with Interdigitated Capacitor

Question asked by user987654321 on Aug 6, 2020
Latest reply on Aug 7, 2020 by user987654321

Anyone have success modeling an interdigitated capacitor in Hyperlynx Decoupling Analysis? It's a single capacitor with 8 pins to lower ESL. 

 

I looked at assigning a PAK but none of the three options (series, pullup, pullup/pulldown) matches the structure. I have a spice model but it's a two-pin and HL wants an 8-pin since that is the package. Any suggestions?

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