Anyone have success modeling an interdigitated capacitor in Hyperlynx Decoupling Analysis? It's a single capacitor with 8 pins to lower ESL.
I looked at assigning a PAK but none of the three options (series, pullup, pullup/pulldown) matches the structure. I have a spice model but it's a two-pin and HL wants an 8-pin since that is the package. Any suggestions?