I am simulating a LPDDR2 800Mb/s interface with a Xilinx Zynq as controller and my simulation fail when I use the timing model I created for the controller.
I will talk about the address bus only (one step at a time).
We used the pin delays for the routing so the delays are the same between the address signals and the clock (from the die of the FPGA to the pin of the memory I have 200ps +/- 5ps for each signal).
When I simulate with the default controller timing model (lpddr2_ctl.v) all the address bus is pass.
But when I use the timing model I created all the address bus is fail.
I used AN10706 to calculate the values, and Example 2 is applicable to the datasheet of Xilinx.
Here are the values from Xilinx:
And the timing diagram between Hyperlynx and Xilinx:
And finally my values in TM Wizard:
Here is an extract of my simulation results:
And the setup / hold time of DDR_A0:
Now my questions
- Why the edge of the clock and the address are aligned? With the same time of flight on each signal I should have the edge of the clock in the middle of the address?
- In the screenshot of the setup time my address is only a half clock period. Is is not a clock period?