1 2 First Previous 19 Replies Latest reply on Jan 6, 2017 9:32 AM by chris_balcom

    Reduce transistor

    andrewng

      Dear All,

       

      Some designers would like to have a checking on LVS which not to reduce any transistors even the split gate.

      That means if there is a transistor which is using W/L: 100/2.

      Layout could not modify the transistor to W/L: 50/2 with 2 fingers.

      How could I modify the setting that this checking is avaliable?

       

      Thanks!

      Andrew

        • 1. Re: Reduce transistor
          chris_balcom

          Hi Andrew,

           

          Do you want to change the settings by changing the rulefile, or is it that you're using Calibre Interactive GUI to start the jobs?

           

          In the rulefile you can change the LVS REDUCE PARALLEL MOS to NO, and you can also change the LVS REDUCE SPLIT GATES to NO. If you don't see those statements in the rulefile you can add the statements to override the default of yes.

           

          If you're using the interactive GUI to run the jobs then you can use the menus to turn that reduction off. Let me know if you need more details.

           

          Best regards,

          -chris

          • 2. Re: Reduce transistor
            andrewng

            Dear Chris,


            I trial with your command and I also added a command for my purpose:

             

            LVS SPICE REPLICATE DEVICES YES

             

            It could solve the problem right now.

            However, I faced another problem is that some IP provider gave us a CDL netlist which could not match with layout they provided.


            Is there any method to check this with different block?

             

            Andrew

            • 3. Re: Reduce transistor
              chris_balcom

              Dear Andrew,

               

              I can appreciate how that statement could be helpful in cases where you did not want to allow reduction of parallel devices.

               

              The statements we discussed earlier prevent reduction of multiple devices in the layout and source but they don't consider devices in the source with the M multiplier property.

               

              By default, the M multiplier property will enlarge the W value of mos devices in the source but there would still be just one device in the source.

               

              For instance, if there was an MN device in the source with W=2 and M=3 then the default behavior is to multiply the width by 3 for a final size of 6.

               

              With LVS SPICE REPLICATE DEVICES YES, the source device will be repeated so that there will actually be 3 separate devices with each width of 2.

               

              Then when you avoid the parallel reduction, the devices can match more consistently even when M property is used.

               

              On the other question I'm not sure I understand the details well enough to offer a suggestion. I wonder why the CDL netlist doesn't match the layout. Are there clues in the LVS report?

               

              I would be interested to learn more about your idea of checking this with another block. Can you tell me more about that?

               

              Best regards,

              -chris

              • 4. Re: Reduce transistor
                andrewng

                Dear Chris,

                 

                Thanks for your reply!
                My case is that some blocks are build from a group of standard cells. Those transistors which used inside the netlist will have a different M property for their layout. It is for their unit height for all cell.

                However, it is too hard to ask the standard cell provider to modify the netlist to fit for the layout. They will think that it is not a MUST for standard cell.

                For this case, could I use any command or setting that I could check these blocks without M property setting?

                 

                Andrew

                • 5. Re: Reduce transistor
                  chris_balcom

                  Dear Andrew,

                   

                  Is it that you want to ignore the M property? you might try using the following rule statement to set the multiplier name to something that doesn't actually exist in the schematic.

                   

                  LVS SPICE MULTIPLIER NAME "nonexist"

                   

                  But that may not work very well with your use of LVS SPICE REPLICATE DEVICES YES.

                   

                  Maybe instead you could just avoid using TRACE PROPERTY M.

                   

                  That may help if you're tracing the M multiplier and just need to stop that part of it so that differences between M multiplier in the layout and source won't be errors.

                   

                  Hope it helps, but I may not understand clearly your situation.

                   

                  Kind regards,

                  -chris

                  1 of 1 people found this helpful
                  • 6. Re: Reduce transistor
                    andrewng

                    Dear Chris,

                     

                    Thanks for your reply!

                    I need to test on it!

                    However, I would like to ask that did you know what is the industrial standard for these setting?

                    It is because I think there will be some problem about dummy transistors which have different W/L which tied together.

                     

                    Best Regards,

                    Andrew

                    • 7. Re: Reduce transistor
                      chris_balcom

                      Dear Andrew,

                       

                      We have a TOLERANCE option to control which devices are allowed to reduce together. We can set the tolerance of the "L" property to "0" if we wish to allow only devices that have the same "L" to be reduced down to a single device.

                       

                      I'm not sure what would be considered the industry standard for those settings. Maybe someone else has an opinion on that?

                       

                      Best regards,

                      -chris

                      • 8. Re: Reduce transistor
                        tan.tran

                        Hi Chris,

                          I have a similar problem with Sharing Source/Drain Cascode layout in LVS in a certain AO Complex Combination Gates  where I have the following property errors which regards to  Multiplier m:,  see below

                        **************************************************************************************************************

                                                              PROPERTY ERRORS

                         

                        DISC#  LAYOUT                                                    SOURCE                      ERROR

                        **************************************************************************************************************

                         

                          1    M2(2.115,0.430)  MN(NMOS_1P8)                             MM1  MN(NMOS_1P8)

                               m: -3.40282e+38                                           m: -3.40282e+38

                         

                          2    M3(2.545,0.430)  MN(NMOS_1P8)                             MM0  MN(NMOS_1P8)

                               m: -3.40282e+38                                           m: -3.40282e+38

                         

                        Now, I tried 2 LVS options setting as followed and theser Multiplier Errors are gone.

                         

                        1) Short Equipotential Nodes together     (This has some risk as it'll potential short some nodes)

                        2) Turn off Reduce Parallel MOS transistors   (I followed this from your suggestion and seems to be working)

                         

                        Could you please tell me which 1) & 2) option above, which one is more recommended and approriate to be used?

                         

                        Thanks

                        Alan

                        • 9. Re: Reduce transistor
                          chris_balcom

                          Hi Alan,

                           

                          I saw your related question come in this morning and I wanted to respond but I wasn't sure I had enough to offer... Here are my thoughts:

                           

                          I'm surprised the property errors are reported even though the properties seem to be identical. The number is very unusual too. -3.40282e+38 ?? Seems more like negative 3 bazillion than a real number for the M multiplier. It makes me wonder how the M property was calculated in these cases. When you short the equipotential gates I suspect the transistors are reduced by split gate reduction and then the M property might be calculated in an effective property calculation section of some LVS REDUCE... statement. If the devices aren't being reduced, then I wonder where that unusual M property value is coming from. Maybe the DEVICE statement? The original M property may show on that device in the netlist extracted from layout during calibre -spice.

                           

                          Hope it helps,

                          -chris

                          • 10. Re: Reduce transistor
                            tan.tran

                            Hi Chris,

                              Thanks for a quick reply.  To be honest, I’m coming from a Hercules User based and try to learn Calibre. I can see the tool behavior are somewhat difference between Hercules & Calibre.  I ran this in Hercules and LVS are clean, no M: multiplier  Errors whereas If I run this in Calibre using Foundry Provided Calibre Rules Deck with the

                            Use Setting From Rules --> Reduce Split Gates --> Reduce Parallel MOS transistors then I have LVS Property Errors with Multiplier (I know, when I look at the M: this numbers are insane) so I’m wondering there is a problem with the LVS Deck itself or there is something about the  Calibre that wasn’t able to recognized a simple  Series Cascode Source/Drain connections. Just to recap on what I’ve tried and either way LVS pass. I’m just looking for a recommendation from you or a Mentor AE expert.

                             

                             

                            1)      I tried  Short Equipotential

                             

                            2)      Turn off Reduce Split Gate as you recommended to the other Users that I saw in the Forum ( LVS passed and Calibre able to extract correct Multiplier M from the Layout).  I’m more inclined toward this setting as it’s safer than 1) Short Equipotential Above.

                             

                                   Could you please confirm or comments on these options?

                             

                            I’ll also attached here a layout which shows where the network of transistors are failing property error with Multiplier along with the corresponding Schematic. Here are a snapshot of the Output CDL from Calibre.

                             

                            MM3 4 A0 16 VPW nmos_1p8 W=880e-9 L=0.180u m=1.0 as=422.4e-15 ad=422.4e-15

                            + ps=2.72e-6 pd=2.72e-6 nrd=0.545455 nrs=0.545455 par=1 dtemp=0

                            MM2 16 A1 VSS VPW nmos_1p8 W=880e-9 L=0.180u m=1.0 as=422.4e-15 ad=422.4e-15

                            + ps=2.72e-6 pd=2.72e-6 nrd=0.545455 nrs=0.545455 par=1 dtemp=0

                            MM1 VSS A1 15 VPW nmos_1p8 W=880e-9 L=0.180u m=1.0 as=422.4e-15 ad=422.4e-15

                            + ps=2.72e-6 pd=2.72e-6 nrd=0.545455 nrs=0.545455 par=1 dtemp=0

                            MM0 15 A0 4 VPW nmos_1p8 W=880e-9 L=0.180u m=1.0 as=422.4e-15 ad=422.4e-15

                            + ps=2.72e-6 pd=2.72e-6 nrd=0.545455 nrs=0.545455 par=1 dtemp=0

                            .ENDS

                             

                             

                            Thanks you Very Much For your help!

                            Tan

                             

                             

                            p.s: If you need any more information, please let me know. I’d be happy to provide.

                            • 11. Re: Reduce transistor
                              chris_balcom

                              Hi Alan,

                               

                              I won't be able to choose between avoiding reduction and turning on split gate reduction (or shorting of equivalent nets - another kind of split gate reduction) because the choice usually depends on what the designer had in mind for the matching of the layout to the schematic. For Calibre, all three possibilities are frequently used by different people to achieve the behavior they want.

                               

                              The weird property values are another story, one that may require more investigation to solve. It's not a typical problem, I don't remember seeing it before. I won't be able to troubleshoot that one here in the communities but you should probably be able to get to the bottom of it by submitting a service request through the Mentor SupportNet website, or maybe digging into it with someone who has experience troubleshooting LVS rulefiles.

                               

                              Sorry I don't have a better answer for you.

                              -chris

                              • 12. Re: Reduce transistor
                                tan.tran

                                Hi Chris,

                                  Thanks for the comments.  Here is what bothering me. From Calibre created Output CDL netlist, I can see the M factor is correct M=1 which match the layout but why

                                Calibre LVS messages saying  m=23e38*  .  I checked the extraction log file, it said succesfullly extract and no warning or anything.  From this I can draw conclusion that internally Calibre are not consistent!!  You know what I mean!!  If I’m getting M=e38 on the Output CDL or atleast a warning on the extraction then I can see where the m=e38 message came from!! How am I suppose to debug something like this?? Even the CDL netlist engine contradict to the Calibre RVE itself!!

                                 

                                Best Regards

                                Tan

                                • 13. Re: Reduce transistor
                                  chris_balcom

                                  Hi Tan,

                                   

                                  I agree it seems crucial to find the reason why that property gets such a strange number. Based on your recent findings I can help by mentioning a good debug technique... adding a few statements so you can see what reduction took place and also the final property values. These statements can be added to your rule file for LVS comparison and the result will be a couple netlists with "after transformation" connectivity and properties:

                                   

                                  LVS WRITE LAYOUT NETLIST tan_layout.spi

                                  LVS WRITE SOURCE NETLIST tan_source.spi

                                   

                                  Then, if there aren't enough clues in the results of those netlists I think you could focus on the LVS REDUCE... statements responsible for the problematic devices. In your rule file there, should be the calculations controlling how the M property would finally be calculated after reduction.

                                  • 14. Re: Reduce transistor
                                    tan.tran

                                    Hi Chris,

                                      Thanks for suggestions.  However, I’m still troubling to understand why I got the correction extraction CDL ouput netlist and Extraction is successful , no warning but Calibre RVE reported differently (m=e38).

                                     

                                    I’d like to find a service request.

                                     

                                    Thanks

                                    Tan

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