For technology nodes above 90nm designers really care only about the following criteria’s: timing requirements, minimal area and power. Since some of these properties are in conflict with each other, designers are forced to make trade-offs between different requirements.
With shrinking geometries situation gets even more complicated as in the sub 90-nm era, design properties quantifying manufacturability becomes important for the whole chip and for standard cells in particular.
Critical area is a main metrics for Yield, it is a key layout attribute based on which we can measure designs sensitivity to yield loss. CA is only dependent on layout and minimum defect size, it means than once analyzing design in terms of CA no needs to re-run analysis flow for different defect densities.CA is the area in the design where failures are most likely to occur. Also for design optimization we need only CA before and after to quantify optimization effect, because the defect density is only a linear scaling of the CA number and all of the CA's scale by the same defect density. You only need defect densities when you combine layers or defect mechanisms. CA parameter can be used for different yield loss mechanisms by applying appropriate defect distribution; in this topic we are going to review only random defect types:
Short: Conductive defect creates an electrical connection between two neighboring wires, defects smaller than min space can’t create short, because particles smaller than spacing min size not able to cover simultaneously two neighbor wires of design.
Open: Non-conductive defect creates an electrical “break” or disconnect in a signal path, defects smaller than min width can’t create open, because particles smaller than min width size not able to break or disconnect a wire.