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RC extraction problem

Question asked by andrewng on Sep 2, 2009
Latest reply on Sep 8, 2009 by samantha_lizak

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Dear all,

Is there any one experienced the same case with me?

Case:

I have a close loop bias transistor which source and body is connected to same power (pls see the attachment). When I extract R of this connection, we found that the resistance is much smaller than by hand calculation (such as extraction result is 29ohms while hand calculation is 59ohm; please note that I haven’t calculate the bias contact). We guess that the small resistance is caused by the diffusion contact which reduces the resistance a lot.

I tried to prove my guessing by setting the sheet resistance of PSD / NSD to 0 ohm/sq. However the results showed no difference. Could anyone give comment on it? Below is my modification in the tech file. Is there any problem in the modification? Do I miss something?

// =================================================

// === Resistance Sheet [Prop_Cnst, Max_Dist] ===

// =================================================

RESISTANCE SHEET NSD [0 0 2.905E-3 -3.686E-7] MASK

RESISTANCE SHEET PSD [0 0 2.949E-3 -4.049E-7] MASK

// ==============================================

// === Resistance Connections [Area, Edge] ===

// ==============================================

RESISTANCE CONNECTION METAL1 NSD [0 0] MASK // Contact

RESISTANCE CONNECTION METAL1 PSD [0 0] MASK // Contact

Best Regards,

Andrew

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andrewng Sep 2, 2009 10:14 PM

Sorry! Forgot to insert the image!

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samantha_lizak Sep 8, 2009 9:15 AM

Hi Andrew-

You don't mention which version of Calibre you are using, so I can only offer suggestions.

1) Because some simulators don't accept 0-value resistors, xRC generally doesn't put them out. (Usually this shows up as them being combined with something else, though.) In older versions, you could force them to be written out by setting the environment variable PEX_INCLUDE_ZERO_R before running. (Technote at http://supportnet.mentor.com/reference/technotes/public/technote.cfm?tn=mg42568 .)

2) "Resistance Sheet" has fairly low priority among the many ways of setting a layer's resistance. Has the foundry also included one of the other statements mentioned in the SVRF manual as overriding Resistance Sheet? If the rule file can also be used for parasitic variation or CMP analysis, chances are good that there is a PEX Table statement for the layer that is used instead. (Most foundries now encrypt their parasitic extraction rules, so you may not be able to see it.)

3) If this is an older version (say, before 2007), you shouldn't use it to do device extraction. Devices are pretty complicated and really require a field solver. Newer versions of xRC are more accurate with devices, but the older versions, developed for larger process nodes, were intended for primarily interconnect effects.

4) Verify that the area of interest hasn't been "cookie-cut" out. In more traditional set ups, the devices are included in as simulation models. To prevent double-counting parasitics, the areas covered by simulation models are excluded from parasitic extraction. Different companies use different methods of doing this. If you use device models that include parasitics, though, that could be happening.

Come to think of it, the initial problem of seeing too high a resistance might be caused by _not_ having "cut out" the device area and causing the resistance to be counted twice. Devices and cookie-cutting are discussed in App Note 0335.

5) If there are aliased layers (PEX Alias or PEX Elayer depending on version), check that the layer isn't being used in PEX Ignore Resistance.

6) If you have a newer version (not sure when it debuted, but likely not before 2008.1) you could try a kludge to temporarily override the setting. The BULKRESISTANCE keyword in PEX Resistance Parameters can be used with non-bulk layers if you comment out the other statements that set resistance. See the SVRF manual for syntax. PEX Table statements (used in rule files that can handle parasitic variation and CMP) still do override this, however.

7) Check how you are reducing parasitic resistance on contacts and vias. Some older reduction methods discarded parasitic resistors below a certain value; I think PEX Threshold was one. If the values are being discarded then making them smaller still has them discarded and you wouldn't see a change.

Good luck-

Sam Lizak

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andrewng Sep 2, 2009 10:14 PM
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Sorry! Forgot to insert the image!
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samantha_lizak Sep 8, 2009 9:15 AM
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Hi Andrew-

You don't mention which version of Calibre you are using, so I can only offer suggestions.

1) Because some simulators don't accept 0-value resistors, xRC generally doesn't put them out. (Usually this shows up as them being combined with something else, though.) In older versions, you could force them to be written out by setting the environment variable PEX_INCLUDE_ZERO_R before running. (Technote at http://supportnet.mentor.com/reference/technotes/public/technote.cfm?tn=mg42568 .)

2) "Resistance Sheet" has fairly low priority among the many ways of setting a layer's resistance. Has the foundry also included one of the other statements mentioned in the SVRF manual as overriding Resistance Sheet? If the rule file can also be used for parasitic variation or CMP analysis, chances are good that there is a PEX Table statement for the layer that is used instead. (Most foundries now encrypt their parasitic extraction rules, so you may not be able to see it.)

3) If this is an older version (say, before 2007), you shouldn't use it to do device extraction. Devices are pretty complicated and really require a field solver. Newer versions of xRC are more accurate with devices, but the older versions, developed for larger process nodes, were intended for primarily interconnect effects.

4) Verify that the area of interest hasn't been "cookie-cut" out. In more traditional set ups, the devices are included in as simulation models. To prevent double-counting parasitics, the areas covered by simulation models are excluded from parasitic extraction. Different companies use different methods of doing this. If you use device models that include parasitics, though, that could be happening.

Come to think of it, the initial problem of seeing too high a resistance might be caused by _not_ having "cut out" the device area and causing the resistance to be counted twice. Devices and cookie-cutting are discussed in App Note 0335.

5) If there are aliased layers (PEX Alias or PEX Elayer depending on version), check that the layer isn't being used in PEX Ignore Resistance.

6) If you have a newer version (not sure when it debuted, but likely not before 2008.1) you could try a kludge to temporarily override the setting. The BULKRESISTANCE keyword in PEX Resistance Parameters can be used with non-bulk layers if you comment out the other statements that set resistance. See the SVRF manual for syntax. PEX Table statements (used in rule files that can handle parasitic variation and CMP) still do override this, however.

7) Check how you are reducing parasitic resistance on contacts and vias. Some older reduction methods discarded parasitic resistors below a certain value; I think PEX Threshold was one. If the values are being discarded then making them smaller still has them discarded and you wouldn't see a change.

Good luck-

Sam Lizak
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