In most digital or mixed-signal design flows, the last step before tapeout is always to assemble a chip with gdsii/oasis files from different sources. This process can take hours to finish if your layouts are big. Now in DESIGNrev, we have the solution. The command is called "layout filemerge" under Tcl interface. In a recent benchmark, it took only 8 minutes to put together a 3Gigabyte Place and Route chip together with its library cells. Same operation can take 2 hours in the place and routing tool.
And the usage is simple:
layout filemerge -in top.gds -in cella.gds -in cellb.gds -in ... -out final_chip.gds -mode overwrite
With this command you can merge the top.gds, cella.gds, cellb.gds and some other cells together and produce a final_chip.gds file. All the cells with the same name will be overwritten by a following input file. And you can change the behavior by changing the mode.
For more information, please check supportNet appNote 10186 use disk-based merger to combine layouts.