Yes, at times I have seen hundreds of false errors during LVS but they seem to happen for different reasons. I can't think of a certain particular reason that is most likely.
Do most of the false errors seem to follow any sort of pattern? Is there anything in common about the errors?
Did the false errors only happen at the top level? Can you get a clean LVS when you run a smaller portion of the layout?
thanks for you answer.
The false errors seem random and spread in all the top level. All cell are OK when checked stand alone. We are trying to change some switch. Maybe we will lucky.
If devices seem to be missing from lower level layout cells, and then extra layout devices at the top level, then that may be caused from seed promotion. Seed promotion can be caused by different things. Calculation of certain properties such as AS/AD are common causes.