0 Replies Latest reply on Oct 2, 2009 4:02 AM by vigen_boyajyan

    How to run memory analysis flow.

    vigen_boyajyan Talented

      Another useful and valuable feature in Yield Analyzer is the memory analysis capability. Memory flow provides a capability to analyze memory cells in the context of chip taking into account the redundancy built in memories.  The main user interface for “Memory Flow” is the memory configuration file. In Calibre Interactive we have file browser for specifying memory configuration file. Memory configuration format has two sections: configuration definition and memory cell declaration.  In first section different memory configurations are declared (sram, dram, etc.). A configuration is basically a name and two separate lists of layer and defect type pairs repairable by column and row redundancy resources correspondingly. For example:

       

      sramConfig = { {DIFF.OPEN} {DIFF.SHORT} {single.odCO} {M1} {single.VIA1} {M2} } { {PO.OPEN}  {single.polyCO} {M1} {single.VIA1} {M2} {single.VIA2} {M3} }

       

      In the first list we have DIFF.OPEN, DIFF.SHORT, single.odCO, M1, single.VIA1 and M2 – meaning short and open failures, single contacts and vias on appropriate layers repairable by redundant columns. In the second list we have second group of layers and appropriate defect mechanism repairable by redundant rows. 

       

      In memory declaration part memory cells names are associated with memory configurations, number of rows, columns, redundant and dummy rows and columns. For example:

      SRAM_S1X22 sramConfiguration 23 1 1025 1 0 1 SRAM_22CC

       

      cellName memoryConfiguration numberOfColumns numberOfRedundantColumns numberOfRows numberOfRedundantRows numberOfDummyColumns numberOfDummyRows bitcellName

       

      Bit cell specification is optional in memory cell declaration.

       

      Using Memory analysis flow designers can measure the impact of redundancy in overall yield loss, to make a decision which solution is acceptable for particular design and technology node.