I have a problem with ic station. I had to make some new standard cells for an application and then to use these cells in an auto-floorplan, auto-route process. I should use auto-floorplan and auto-route for my circuit because it is too large for placing and routing the cells manually. My problem is that when I use auto-floorplan in ic station with my circuit netlist created in da_ic from a VHDL code, I see the green rows and my cells appear correctly inside the rows but my cells' ports and the overflows connecting them are missing.
I'm sure nothing is wrong with my cells because they all pass the DRC & LVS checks and their ports has been created the same way explained in mentor graphic tutorial "Schematic Driven Layout using the ADK v3.1". Please tell my why I face this problem or if you have good tutorials for making new standard cells and using them in an auto-floorplan process please email their links to my email email@example.com.