4 Replies Latest reply on Jan 9, 2010 12:26 AM by yu.yanfeng

    Does HL 8.1 Beta 2 support to analysis DC Drops in Full ower-ground

    yu.yanfeng

      Simultaneous power and ground net simulation during DC-drop and current density analysis/documents/Decoupling_Lab.zip

        • 1. Re: Does HL 8.1 Beta 2 support to analysis DC Drops in Full Power-Ground Loop?
          yu.yanfeng

          Does HL 8.1 Beta 2 support to analysis DC Drops in Full Power-Ground Loop?

          I installed this beta2 and found no way to do this in the tool.

          In the beta2's new features list, I see "Simultaneous power and ground net simulation during DC-drop and current density analysis".

          Thanks.

           

          Yanfeng

          • 2. Re: Does HL 8.1 Beta 2 support to analysis DC Drops in Full ower-ground
            Steve_McKinney

            Hi Yanfeng,

             

            Yes it does support simulation of the full path through the power net and the reference net (ground).  When you open up the DC Drop tool, there is a checkbox for "Include Reference Net(s)" right under where you select the net you want to analyze.  If you select that, the reference net will be included in your simulation.

             

            -Steve

            • 3. Re: Does HL 8.1 Beta 2 support to analysis DC Drops in Full ower-ground
              yu.yanfeng

              Hi Steve,

              Much thanks!

              I only checked this feature in PDN editor, forgot to check this feature in the boardsim. Now, I found this option in the board, it seems something is wrong in the tool.

              Attached is the testcase,decryption password see the mail.

              Yanfeng

              • 4. Re: Does HL 8.1 Beta 2 support to analysis DC Drops in Full Power-ground Loop
                yu.yanfeng

                Hi Steve,

                 

                After adjusting the boundary of the refence net's plane shape to cover all IC's Power/Ground pins, It can do the dc-drop analysis in full loop. I guess the software first check this boundary to see wether all related Power and Ground pins within it before allowing user to assign the refrence net  to the VRM.  I understand the importance of this check to the Algorithm.  But,  in real design,  the Power/Ground pins of some comonents (which be routed ) in the VRM circuit are  out of the boundary, so user cann't do a full loop analysis due to this limitation.  I hope you can forward this issue to HL Engineering team.

                 

                Because increasing power dissapation in PCB, User need a powerful and easy-to-use PI tool to verify the design, to see where are the hottest, how much drops over the loop. During past years, We see more ten  PBA be burned out in the field due to poor design of the power rail.

                 

                In tthe DC analysis of full board, both the solver Speed an the results rending /graphics updating are important to user'experence. I hope HL engineering team make the solver to support multiple threads, also make this tool more mature. We hope we can deploy this tool to engineer's desktop by 2010 end.

                 

                 

                 

                 

                1.GIF

                 

                 

                 

                 

                Yanfeng