I have to find out by automation, if a via, wich is placed in a package cell, was replaced by another via padstack with padstack processor.
We have added the vias in Cell Editor to the package and placed underneath the center pad, to ensure a good ground connection of the LGA.
But in some cases we have seen, the those vias were replaced interactively by a layouter with padstack processor, although the replacement via padstack is not allowed to be used here.
The following solution approaches are not working here:
- setting the via type as allowed via in CES for this specific net (the same net has other defaoult vias somewhere else)
- drawing a rule area around the LGA and setting th evia as via type for the net in this specific rule area (too much effort of drwaing and maintaining new rule areas constraints around LGAs)
- locking the via in Cell Editor (does not help; via can be changed anway)
So I would like to know, if someon has an idea to find out, if a via on a component in the design is different to the via defined on the cell in the cell database.
We checked the vias component and saw, that the replacemnt via also belongs to the component. This relationship has not been lost by padstack processor.
But the padstack is not modified in any way.
What we are looking for is such a functionallity, wich tells my if the design elements of a cell are modified compared to the original one in the design cell database.