6 Replies Latest reply on Jun 1, 2010 10:50 AM by karen_chow

    Calibre xRC, PEX setup for 65nm IBM


      My name is Felipe Werle and I work in the microelectronic lab in my university (UFRGS -
      Universidade Federal do Rio Grande do Sul) in Porto Alegre, Brasil.
      Right now we are working with IBM cmos10lpe in 65nm, cadence I6.1.3, design kit V4.1.0 
      and calibre v2008.4_36.26 for DRC LVS and xRC.
      And I can't extract my circuits with calibre xRC. I have already include de LVS.cal in my
      cmos10lpe_"deck"_6_02_00_00_LB_"detail".xrc.cal to make the rule file for PEX. But it
      didn't work, when I select to load this file it find one error like SYN8 on line 91? ?
      unpaired left brace (/{)or right brace(}/)?
      I don't really know what is wrong; I read that I should include LVS.cal in the xrc.cal file.
      Could you please send me a tutorial to run and setup PEX with this Calibre, this
      technology and this cadence? I have already search in the web but didn't found anything
      that help me.

      Do you know how to set calibre PEX in this tecnology?

      Thank you.

      Felipe Correa Werle