1 Reply Latest reply on May 13, 2010 3:51 PM by chris_balcom

    Calibre LVS: Verilog Netlist VS layout?

    zhen.boston

      Hello, everybody:

       

      Recently I'm using calibre to do LVS in virtuoso for layout imported from  encounter. The library I'm using is NANGATE 45nm library.


      The design is placed and routed in encounter and then saved as oa design, which can be opened in virtuoso.


      Calibre DRC is all clear. When I try to do LVS, one input file is the openaccess layout view in virtuoso. I would like to use an verilog netlist as the other input file. However, the following errors occur. (The design was simply a counter. )

       

      ------------------------------------------------------------------------------------------------------------

      Error: No matching ".SUBCKT" statement for "CLKBUF_X2" at line 5 in file *************
      Error: No matching ".SUBCKT" statement for "INV_X16" at line 6 in file *************
      Error: No matching ".SUBCKT" statement for "INV_X32" at line 7 in file*************
      Error: No matching ".SUBCKT" statement for "DFF_X2" at line 8 in file *************
      Error: No matching ".SUBCKT" statement for "NOR2_X2" at line 9 in file *************
      Error: No matching ".SUBCKT" statement for "DFF_X2" at line 10 in file *************
      Error: No matching ".SUBCKT" statement for "XNOR2_X2" at line 11 in file *************
      Error: No matching ".SUBCKT" statement for "NOR2_X2" at line 12 in file*************

      ------------------------------------------------------------------------------------------------------------

       


      The .v file I used as netlisis as follows.It is a structural description of the counter generated by the encounter. Is this the right file I should use for LVS? Or do I need to generate another netlist file?

       

      --------------------------------------------------------------------------------------------------------

      // Generated by Cadence Encounter(R) RTL Compiler v07.10-s016_1
      module counter (
          out,
          clk,
          reset);
         output [1:0] out;
         input clk;
         input reset;

       

         // Internal wires
         wire FE_PHN0_reset;
         wire clk__L2_N0;
         wire clk__L1_N0;
         wire n_0;
         wire n_1;
         wire n_2;

       

         CLKBUF_X2 FE_PHC0_reset (.Z(FE_PHN0_reset),
          .A(reset));
         INV_X16 clk__L2_I0 (.ZN(clk__L2_N0),
          .A(clk__L1_N0));
         INV_X32 clk__L1_I0 (.ZN(clk__L1_N0),
          .A(clk));
         DFF_X2 \out_reg[1]  (.Q(out[1]),
          .D(n_2),
          .CK(clk__L2_N0));
         NOR2_X2 g29 (.ZN(n_2),
          .A2(reset),
          .A1(n_1));
         DFF_X2 \out_reg[0]  (.Q(out[0]),
          .D(n_0),
          .CK(clk__L2_N0));
         XNOR2_X2 g31 (.ZN(n_1),
          .B(out[1]),
          .A(out[0]));
         NOR2_X2 g32 (.ZN(n_0),
          .A2(FE_PHN0_reset),
          .A1(out[0]));
      endmodule

       

      ---------------------------------------------------------------------------

       

      Thanks for all your help~!

       

      Best Regards~


      Zhen

        • 1. Re: Calibre LVS: Verilog Netlist VS layout?
          chris_balcom

          Hi Zhen,

           

          It looks like you might be missing some spice library information... the subckt definitions for those cells such as NOR2_X2 and INV_X16.

           

          Can you get to the Calibre Interactive Users Manual for version 2010.1 ? If you search for the phrase "setting up the verilog translator" you should be taken to some step by step details about how to include a spice library.

           

          Will you let us all know if that works, or what variation actually solved the problem?

           

          Best regards,

          Chris