11 Replies Latest reply on Nov 29, 2012 8:23 AM by artwork.master1

    I/O Designer in a PADS Flow - opening questions


      Dave & Frank,


      Thanks for taking the time & effort to set this discussion thread up.  In the many customer interactions I have encountered, high pin count FPGAs devices are definitely a challenge to a lot of teams.  And seeing as this is a flow neutral board - let's kick things off with a PADS Flow topic...


      Design Teams using the PADS Flow traditionally are built on the foundation of smaller to medium size organizations where team members wear multiple hats (librarian & designer all-in-one is very common).  In this environment, designers are used to building flat symbols based on banking structures of the FPGAs to reduce symbol development time.  It is basically a - create it once & never change it strategy.  How best would you describe I/O Designer replacing or augmenting a structure like this?


      Is the potential process change worth the effort?





        • 1. Re: I/O Designer in a PADS Flow - opening questions



            The best process to work with flat designs is our I/O Designer "Schematic Update Flow".  Unfortunately, we have not released the schematic update flow for the DxDesigner - PADS flow yet (but that is scheduled to change for the next PADS release).


            You may create the FPGA symbols (or "symbols" for pin bank based fractures) manually or by leveraging the automation within I/O Designer (IOD).  Personally, I reccomend using I/O Designer to generate the pin bank fractured symbols as it is very fast and insures that you have not omitted any pins.  Once you have the symbols created you follow your normal process of creating a complete part (including the footprint).


            The nice thing about the schematic update flow is that has a very minimal impact on the design process... you instantiate the FPGA symbol ("symbols" if you use fractured symbols for the FPGA) as you would do normally.  The benefit to the design process is two fold:


          1. I/O Designer will automatically "wire up" the FPGA symbols based on the interface design for the FPGA --- and will update the schematic if you change the interface or when you use the I/O Designer unraveling.

          2. Once I/O Designer has been introduced into the flow the key benefit is leveraging the flexibility of the FPGA's pin configuration to optimize the PCB for trace length (make traces shorter) and to minimize trace cross-over (huge reduction in the number of vias on the PCB).



          Is it "worth the effort"? => Heck Yes!! (I would have used some stronger language but I do not want to violate our policy guidelines )  If you are using FPGAs in your design and your are NOT using I/O Designer you are making your PCB routing task significantly more complicated than it needs to be!  Customers are typically reporting 40% - 60% reduction in total design time when using IOD compared to when  they were not using IOD. (So, if time to market is worth money to you,  or meeting that "arbitrary management deadline" has value to your professional growth --> I strongly encourage consideration of I/O Designer in your design flow.)




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          • 2. Re: I/O Designer in a PADS Flow - opening questions



            Also wanted to understand the differences between the flat & hierarchical approach in a PADS Flow.  As most designers are familiar with flat design process we can start there...


            Flat design methodology allows designers to create set of static symbols, stored in a central location available to all designers, that can be used across many designs and "hooked up" based upon the unique usage of the FPGA within a design.  This reduces the symbol modification iterations and allows engineers to focus on connectivity on a familiar symbol set.


            The hierarchical approach is slightly different.  This introduces a set of local "functional" symbols that represent a high level functions within the FPGA code.  This implementation specific functional symbol will usually stay constant (within a design) even when I/O changes.  The "PCB-ready" symbols are then dynamically created (sometimes several times throughout the process) on a schematic sheet underneath this functional symbol.  In this process designers adjust to manage local symbols & looking at data through a hierarchical view.


            Can you talk a little about the pluses / minuses of each & sharing based on your experience which of these methodologies provides the greatest value to a design team?





            • 3. Re: I/O Designer in a PADS Flow - opening questions

              Hi John and Dave,


              I'm having difficulties to import the PADS Layout design in I/O Designer with the current PADS9.1 flow.


              When using the workshop material IOD_DxD_PADS_Workshop v7.1.pdf and upgraded this to the latest PADS 9.1 version.


              I'm as far as page 28, where I forward annotated the added ImageProc FPGA to the existing PADS Layout database "optimizing_board.pcb."

              Now I expected that I can load this pcb into the I/O Designer environment after having added a New Layout to the project using File | Add to Design | New Layout.


              But the Import | Layout stayes grayed out!!!! Having installed the 9.0.1SDD_SAT, PADS-Expedition translator as well and added the ppcb2hkp.exe to the preferences...


              Not sure what todo more, any suggestions.


              Best regards,

              Bas Hassink, InnoFour.

              • 4. Re: I/O Designer in a PADS Flow - opening questions

                If you are using the newest I/O Designer will need to use the RMB (Right Mouse Button) in the project area then select "Project Properties".  There you can associate the board w/ the project.


                Let me know if that helps.



                • 5. Re: I/O Designer in a PADS Flow - opening questions

                  Hi John,


                  Thanks for the reply.... That's indeed doing the job.


                  Another question? Did you see this behavior before, the rotation of the connectors are not read correctly. See attached image.




                  • 6. Re: I/O Designer in a PADS Flow - opening questions


                    This is a bug and similiar issue was fixed already for the next PADS release that is comming soon.

                    IOD recalculated components rotation in a wrong way before for the PADS layout.


                    Iza Kwiecien

                    • 7. Re: I/O Designer in a PADS Flow - opening questions

                      i have a pcb already placed in Pads and with the assignement of pins swappable build directly inside the components that i use in the pcb.

                      (my schematic was orcad and i use only the netlist to pack the pcb in Pads.)

                      You can consider these bgas like custom parts.

                      My question is:

                      Can i import the pcb inside the I/O Designer and use its capabilities to swap the pins of the Bga using only the intelligence of the swappability already builded inside the parts?

                      Can i use its (I/O Designer)  power to unravel the rastnet? even if the traces (breakout are already designed in the Layout) are attached to the swappable pins of the Bga?


                      Can i save after the unravelling the new pcb in pads format? or have a report of the new signal attached to the pins of the bga? or a sort of eco changes?


                      thanks for any reply.


                      • 8. Re: I/O Designer in a PADS Flow - opening questions

                        Hello Livio,


                        To clarify I/O Designer optimizes connectivity, nets connected to FPGA part defined in FPGA database in I/O Designer. During unravel process I/O Designer takes into account set of constraints which are defined either in FPGA libraries and in implemented predefined rules for FPGA vendors. I/O Designer does not touches layout kind objects like traces, the algoritm analyses situation in the layout and if it is possible it unravels netlines to end of partially routed traces connected to FPGA pins (fanouts/breakouts). Regarding to saving new version of PCB, instead of doing this (as I/O Designer does not modify layouts directly - always indirectly) all unravel optimization results are reflected in assignemnts in FPGA database in I/O Designer which is used to update connectivity on schematic and then all changes can be forward-annotated to layout. All changes done in IOD are reflected in Console and log file, you can also compare P&R constraint files (was/is) or implement any other mechanism using TCL scripting.


                        Thank you.

                        Best Regards,


                        • 9. Re: I/O Designer in a PADS Flow - opening questions

                          So after your explanation my new question is: can i add the swappability of my chips to a new definition of Fpga so the program can use it to know how to swap the pins?

                          In other words is it possible create a new Fpga and add it to the libraries? If so how?

                          thanks for your reply.


                          • 10. Re: I/O Designer in a PADS Flow - opening questions

                            Hello Livio,


                            I/O Designer offers limited capability to edit FPGA devices which exist in I/O Designer FPGA libraries for 4 FPGA vendors like Actel, Altera, Xilinx and Lattice.There is no possible to define own cell definition which does not exist in I/O Designer libraries.


                            What I/O Designer allows users is to add additional set of contraints (rules) on the top of predefinied rules in Rule Editor to give users more control on the tool to apply specific, required assignment strategies.


                            Thank you.

                            Best Regards,


                            • 11. Re: I/O Designer in a PADS Flow - opening questions

                              Thanks for your answer.

                              I hope that in the future you amply the capabilities of IO Designer to read the swappability inside the components of the database (pcb) so to augment the possibility to use its capabilities and open its market.