Dave & Frank,
Thanks for taking the time & effort to set this discussion thread up. In the many customer interactions I have encountered, high pin count FPGAs devices are definitely a challenge to a lot of teams. And seeing as this is a flow neutral board - let's kick things off with a PADS Flow topic...
Design Teams using the PADS Flow traditionally are built on the foundation of smaller to medium size organizations where team members wear multiple hats (librarian & designer all-in-one is very common). In this environment, designers are used to building flat symbols based on banking structures of the FPGAs to reduce symbol development time. It is basically a - create it once & never change it strategy. How best would you describe I/O Designer replacing or augmenting a structure like this?
Is the potential process change worth the effort?