As my initial post, taking this opportunity to welcome everyone to the "I/O Designer Insiders" community, and introduce myself. To a number of you, this is a manner of re-introduction, as I spent 8+ years spanning two decades in field applications engineering at Mentor Graphics, supporting new customer installations of our Printed Circuit Board solutions.
Since then, I (Frank Smetana, pictured) have carried account management roles initially focused on ASIC Design at Synopsys, and opened up new territories for Synplicity as FPGA starts increased, overtaking now past an order of magnitude. Appropriate then, to coalesce these experiences into the role I was installed in at the first part of the year as Market Development Manager for I/O Designer.
Appropriate also, as the burgeoning trends of integration of multiple CPU cores, multiple protocol IP cores, and real-world signaling at the pins of the device at 10Gb/s plus, combined with packages approaching 2000 pins, have pushed pin assignment, symbol/schematic creation/update, and I/O swapping to bottlenecks costing additional schedule weeks/months and additional PCB layers. New challenges to make all our lives more interesting inside and outside the pins. As many of you know, we provide rules-driven, correct-by-construction connectivity models. One of my responsibilities is FPGA Vendor relationships, and will post with updates.
I hope you enjoy the I/O Designer Insiders Community. Feel free to use the community to network with peers, exchange tips, pose questions, share industry news, offer opinions, etc.
Looking forward to lively discussion, as Dave Brady and I will alternate posts and responses depending upon area of expertise and responsibility.