3 Replies Latest reply on Jun 4, 2010 11:17 AM by chris_balcom

    lvs issue

    tanu

      Hi All,

       

      I have an issue in lvs.

       

      The std cell cdl netlist I am using for lvs has diodes using different ground (GND!) and it is mentioned as GLOBAL.

      Here is the cdl file

      ****
      .GLOBAL GSUB!
      ****
      .SUBCKT an2x0_a V G A1 A2 O
      MM5_LP G U3_IN O G N5V W=1u L=600n M=1
      MM6 G A2 U2U7_DRN G N5V W=1.1u L=600n M=1
      MM4 U2U7_DRN A1 U3_IN G N5V W=1.1u L=600n M=1
      DKM4 G V KH AREA=3.7752e-11
      DJM4 GSUB! V JH AREA=2.51056e-10
      MM2_LP V U3_IN O V P5V W=2u L=600n M=1
      MM3 V A2 U3_IN V P5V W=1.4u L=600n M=1
      MM1 U3_IN A1 V V P5V W=1.4u L=600n M=1
      DJM1 GSUB! V JH AREA=5.8476e-11
      .ENDS
      ****

       

       

       

      But the std cell gds does not have port names as GND!...The basic power & ground for the design is V & G.

       

      when i run lvs it is showing as follows

       


      **************************************************************************************************************
                                         INCORRECT PORTS

      DISC#  LAYOUT NAME                                               SOURCE NAME
      **************************************************************************************************************

        1    ** missing port **                                        GSUB! on net: GSUB!

       

       

       

      did any see such issue.It is 180nm technology...Please some one help me with this issue..this is urgent and I need my LVS clean..

        • 1. Re: lvs issue
          chris_balcom

          Hi Tanu,

           

          There may be several different ways to deal with this. I can suggest one or two, maybe someone else can improve on my suggestion, especially if they have experience with the same std cells.

           

          This should only be a problem while you run LVS on the standard cell all by itself, right? I would expect this to be okay as is, once you run larger cells that contain this standard cell. My expectation is that the "GSUB!" port exists for the source CDL because it is declared as .GLOBAL in the netlist and Calibre default rulefile setting is "LVS GLOBALS ARE PORTS YES".

           

          The layout port may not exist if PORT LAYER TEXT is missing for the "GSUB!" net in the layout standard cell.

           

          So in summary:

           

               You might stop creation of the source port by using LVS GLOBALS ARE PORTS NO.

           

               or

           

               You might force creation of a layout port by adding a text object that works with PORT LAYER TEXT in the rulefile.

           

               or

           

               You may choose to run LVS on higher level cells instead of running it just on the standard cell by itself.    

           

          Will you let us know what works if you find a solution?

          1 of 1 people found this helpful
          • 2. Re: lvs issue
            tanu

            Hi Chris,

             

            Thanks for your response..It was really help ful.

             

            Indeed i am running block level lvs where I am using the std cells.

             

            I used LVS GLOBALS ARE PORTS NO option and it worked magic...but only concern is when i using the hcell list it would not work

             

            If i don't use hcell list then the report is clean..But the moment I use hcell list the result is not INCORRECT and all the std cells are coming INCORRECT too.the report looks something like this(top level)

             

            **************************************************************************************************************
                                             INCORRECT INSTANCES

             

            DISC#  LAYOUT NAME                                               SOURCE NAME
            **************************************************************************************************************

             

              2    D0(0.800,3.790)  D(JH)                                    ** missing instance **

             

            --------------------------------------------------------------------------------------------------------------

             

              3    X249/D1(3.600,30.840)  D(KH)                              ** missing instance **

             


            **************************************************************************************************************
                              INSTANCES OF CELLS WITH NON-FLOATING EXTRA PINS

             

            DISC#  LAYOUT NAME                                               SOURCE NAME
            **************************************************************************************************************

             

              4    X246/X7717(439.700,241.390)  delx1_a                      XFE_PHC4_ADCREF_EN_DEL  delx1_a
                     ** missing pin **                                         GSUB!:GSUB!

             

            --------------------------------------------------------------------------------------------------------------

             

              5    X246/X7714(138.740,261.190)  delx1_a                      XFE_PHC5_FLED1_EN_DEL  delx1_a
                     ** missing pin **                                         GSUB!:GSUB!

             

            --------------------------------------------------------------------------------------------------------------

             

             

             

            and for the individual cells i am getting this

            **************************************************************************************************************
                                             INCORRECT OBJECTS
            **************************************************************************************************************

             

             

             


            LEGEND:
            -------

             

              ne  = Naming Error (same layout name found in source
                    circuit, but object was matched otherwise).

             


            **************************************************************************************************************
                                               INCORRECT NETS

             

            DISC#  LAYOUT NAME                                               SOURCE NAME
            **************************************************************************************************************

             

              1    ** missing net **                                         GSUB!

             


            **************************************************************************************************************
                                             INCORRECT INSTANCES

             

            DISC#  LAYOUT NAME                                               SOURCE NAME
            **************************************************************************************************************

             

              2    ** missing instance **                                    DKM4  D(KH)

             

            --------------------------------------------------------------------------------------------------------------

             

              3    ** missing instance **                                    DJM1  D(JH)

             

             

             

            Please let me know if you know the reason....Appreciate your response

            • 3. Re: lvs issue
              chris_balcom

              Hi Tanu,

               

              I don't think the LVS GLOBALS ARE PORTS statement relates to this block level LVS report in the most recent post. I expect that statement to have an effect when you run the standard cell all by itself.

               

              The symptoms "missing device" and "non-floating extra port" can mean different things at different times but I have a feeling for what is happening in your case.

               

              The "missing devices" in the source (from the report for the higher level cell), indicate to me that the diodes may have been promoted out of the lower layout cell, and up to the higher level. There can be different causes for that. I don't have enough details to know what the cause was in your case. I think there are TechNotes on various causes you should be able to find searching http://supportnet.mentor.com

               

              The "missing devices" in the layout (from the report section for the lower level cell) should be just another way of thinking about the same problem I mentioned above.

               

              The "non floating extra pins" can mean different things at different times. sort of... It always means there is a connection to a cell on one side, that isn't on the other side, but that can have different causes. For instance, if there is an unintentional short in the layout from a wire, to a cell, then that connection becomes a pin on the layout cell. That is an extra pin (because it's not there in the source), and it's non-floating because this extra pin actually connects to something outside the cell.

               

              In your case I think the non-floating extra pin warning is simply related to the diode that was promoted out of the lower level cell. Since the diode is gone from the lower level layout, there is no pin to that diode in the layout for the cell, but the pin is still there in the source, and it's connected in the source, so it is reported as a non-floating extra pin. But really the basic problem was that the diode is not where it was expected to be.

               

              So all these problems would likely be cleared up by dealing with that diode that isn't at the right hierarchical level during LVS.

               

              If you stop using it as an HCELL, then the hierarchy for the cell won't matter anymore, and for many people that would be the ideal fix.

               

              If you don't want to just drop it from the hcell list, you may then need to work through the cause of the diode promotion so that it stays in the cell. Whether that is even practical or not depends on the reason for the seed promotion. Sometimes it's layer derivations, higher level layers in the layout, or property calculations that can't have the same answer for every placement of the cell, or properties that weren't even really needed for the LVS.