AnsweredAssumed Answered

lvs issue

Question asked by tanu on Jun 3, 2010
Latest reply on Jun 4, 2010 by chris_balcom

Hi All,


I have an issue in lvs.


The std cell cdl netlist I am using for lvs has diodes using different ground (GND!) and it is mentioned as GLOBAL.

Here is the cdl file

.SUBCKT an2x0_a V G A1 A2 O
MM5_LP G U3_IN O G N5V W=1u L=600n M=1
MM6 G A2 U2U7_DRN G N5V W=1.1u L=600n M=1
MM4 U2U7_DRN A1 U3_IN G N5V W=1.1u L=600n M=1
DKM4 G V KH AREA=3.7752e-11
DJM4 GSUB! V JH AREA=2.51056e-10
MM2_LP V U3_IN O V P5V W=2u L=600n M=1
MM3 V A2 U3_IN V P5V W=1.4u L=600n M=1
MM1 U3_IN A1 V V P5V W=1.4u L=600n M=1
DJM1 GSUB! V JH AREA=5.8476e-11




But the std cell gds does not have port names as GND!...The basic power & ground for the design is V & G.


when i run lvs it is showing as follows


                                   INCORRECT PORTS

DISC#  LAYOUT NAME                                               SOURCE NAME

  1    ** missing port **                                        GSUB! on net: GSUB!




did any see such issue.It is 180nm technology...Please some one help me with this issue..this is urgent and I need my LVS clean..