When To Use IOD's Multi-FPGA Optimization Option?

Discussion created by dave_brady on Jun 11, 2010

It is very common for a design to contain more than one FPGA.  Every once in a while a customer will ask if they need the Multi-FPGA Optimization engine option and my typical response is that if you are using three of more FPGAs in your design you need the Multi-FPGA Optimization engine option.  Then I ask some questions about the design and make a more specific recommendation.


The real issue to be considered when looking at the need of the Multi-FPGA optimization engine option is the connectivity between the FPGAs.  If you have many FPGAs in the design but they are not connected to each other than the need for the Multi-FPGA optimization engine decreases significantly. Don't take this comment the wrong way... The Multi-FPGA optimization engine will still save you time in this design configuration but you will be able to achieve the same quality of results optimizing one FPGA pinout at a time.


  If you have two FPGAs that are strongly connected to each other in the design you may optimize the pinout for one of the FPGAs "stand alone", optimize the second FPGA's pin out "stand-alone" and then probably optimize the first FPGA pin-out one last time.  The quality of results will converge.


  However, when you have three or more FPGAs in the design and they are strongly connected to each other the "one at a time" pinout optimization process closely resembles chasing a jack-rabbit in a wide open field....  It is very difficult to achieve the highest quality of results as an optimization pass on one FPGA has a direct impact to the optimization of the pin-outs on the two (or more) other FPGAs.  This is where the IOD muti-FPGA optimization engine really shines... it has the ability to systematically optimize the pinouts on multiple FPGAs simultaneously by analyzing the connectivity to avoid the "chasing your tail" challenge associated with the "one at a time" process.


  Obviously, there are strategies that could be employed by the designer to achieve high quality pinout optimization results that will reduce trace length, trace cross-overs, via count and improve design performance using the "one at a time" approach for multi-FPGA designs.  By analyzing the connectivity the user selects the "most connected" FPGA for first pass optimization, and then moves down the list of FPGA to FPGA connectivity to process each FPGA in order.  This will still result in the need to optimize some of the FPGAs more than once (typically the highly connected FPGA to FPGA components will require a second pass) and you are able to achieve acceptable results (although they may not be the "best" results).  The process relies on the design engineers ability to visualize the connectivity pattern between FPGAs and select the correct optimization order (in some cases this is trivial... in some cases this is a mind numbing exercise).


  Let's face it, there are some problems that are better solved by the application of computer processing then human processing and when you are dealing with multiple-FPGA design with strong connectivity between three or more FPGAs the computer is able to process more combinations in a shorter amount of time than the human brain.  This is why we created the Multi-FPGA optimization engine option for I/O Designer... not only does it save a huge amount of time in the design process it is able to find solutions that are very difficult to visualize when you view the rats nest of connectivity between high pin count FPGA devices.