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calibre lvs converting verilog to spice

Question asked by eng.marwa_ahmed on Jun 23, 2010


i'm in an ASIC design project .. i use synopsys for synthesis, first encounter for placement and routing , and calibre for drc/lvs

i have some questions about calibre :

what is the importance of the stream_in file?

how can i add the .lef format  (technology file of tsmc090 used in the first encounter run )?

how can i add slow.db ( database file used in synopsys ) ?

must i add them ?

or only the svrf rule file is the important one ?


for the lvs run :

the verilog file output from the first encounter is what i have ! is it the correct input ?

in this case i must convert it to spice by v2lvs ?

i tried to convert it using the command :

v2lvs -v <verilog.v>  -o   <netlist_extracted.spi>    //words between <> is an arbitrary name only

but i had this error :

Creating Design Database ...
Converting Design ...
Warning: no module declaration for module ADDHXL first encountered in module IFFT_PTS_1_DW01_inc_6_0_0

....same warning for all cells .


how can i correct this plz ? how can i have a correct lvs run ?


thx for helping me